Loading drivers/gpu/msm/adreno_a6xx.c +2 −2 Original line number Diff line number Diff line Loading @@ -2667,7 +2667,7 @@ static int a6xx_enable_pwr_counters(struct adreno_device *adreno_dev, if (!device->gmu.pdev) return -ENODEV; kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0); kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xFF000000); kgsl_regrmw(device, A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xFF, 0x20); kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0x1); Loading drivers/gpu/msm/kgsl_gmu.c +6 −8 Original line number Diff line number Diff line Loading @@ -1405,14 +1405,12 @@ int gmu_start(struct kgsl_device *device) if (ret) goto error_gpu; if (gmu->wakeup_pwrlevel != pwr->default_pwrlevel) { ret = gmu_dcvs_set(gmu, gmu->wakeup_pwrlevel, pwr->pwrlevels[gmu->wakeup_pwrlevel] .bus_freq); pwr->pwrlevels[gmu->wakeup_pwrlevel].bus_freq); if (ret) goto error_gpu; gmu->wakeup_pwrlevel = pwr->default_pwrlevel; } break; case KGSL_STATE_RESET: Loading Loading
drivers/gpu/msm/adreno_a6xx.c +2 −2 Original line number Diff line number Diff line Loading @@ -2667,7 +2667,7 @@ static int a6xx_enable_pwr_counters(struct adreno_device *adreno_dev, if (!device->gmu.pdev) return -ENODEV; kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0); kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xFF000000); kgsl_regrmw(device, A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xFF, 0x20); kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0x1); Loading
drivers/gpu/msm/kgsl_gmu.c +6 −8 Original line number Diff line number Diff line Loading @@ -1405,14 +1405,12 @@ int gmu_start(struct kgsl_device *device) if (ret) goto error_gpu; if (gmu->wakeup_pwrlevel != pwr->default_pwrlevel) { ret = gmu_dcvs_set(gmu, gmu->wakeup_pwrlevel, pwr->pwrlevels[gmu->wakeup_pwrlevel] .bus_freq); pwr->pwrlevels[gmu->wakeup_pwrlevel].bus_freq); if (ret) goto error_gpu; gmu->wakeup_pwrlevel = pwr->default_pwrlevel; } break; case KGSL_STATE_RESET: Loading