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Commit 51c0e87e authored by Wei Yang's avatar Wei Yang Committed by Michael Ellerman
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powerpc/eeh: Cache normal BARs, not windows or IOV BARs 



This restricts the EEH address cache to use only the first 7 BARs. This
makes __eeh_addr_cache_insert_dev() ignore PCI bridge window and IOV BARs.
As the result of this change, eeh_addr_cache_get_dev() will return VFs from
VF's resource addresses instead of parent PFs.

This also removes PCI bridge check as we limit __eeh_addr_cache_insert_dev()
to 7 BARs and this effectively excludes PCI bridges from being cached.

Signed-off-by: default avatarWei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: default avatarGavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 971427f5

arch/powerpc/kernel/eeh_cache.c

+5 −6
Original line number Diff line number Diff line
@@ -195,8 +195,11 @@ static void __eeh_addr_cache_insert_dev(struct pci_dev *dev) 
		return;

	}



	/* Walk resources on this device, poke them into the tree */

	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {

	/*

	 * Walk resources on this device, poke the first 7 (6 normal BAR and 1

	 * ROM BAR) into the tree.

	 */

	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {

		resource_size_t start = pci_resource_start(dev,i);

		resource_size_t end = pci_resource_end(dev,i);

		unsigned long flags = pci_resource_flags(dev,i);
@@ -222,10 +225,6 @@ void eeh_addr_cache_insert_dev(struct pci_dev *dev) 
{

	unsigned long flags;



	/* Ignore PCI bridges */

	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)

		return;



	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);

	__eeh_addr_cache_insert_dev(dev);

	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);