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Commit 515b2392 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: write D_COMP using the mailbox 



You can't write it using the MCHBAR mirror, the write will just get
dropped.

This should make us BSpec-compliant, but there's no real bug I could
reproduce that is fixed by this patch.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
[danvet: Fix spelling mistake in the comment that Damien spotted.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 507c1a45

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -1441,6 +1441,8 @@ 
 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in

 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in

 * every way.  It is not accessible from the CP register read instructions.

 * every way.  It is not accessible from the CP register read instructions.

 *

 *

 * Starting from Haswell, you can't write registers using the MCHBAR mirror,

 * just read.

 */

 */

#define MCHBAR_MIRROR_BASE	0x10000

#define MCHBAR_MIRROR_BASE	0x10000
@@ -4724,6 +4726,8 @@ 
#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9

#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9

#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4

#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4

#define	  GEN6_PCODE_READ_RC6VIDS		0x5

#define	  GEN6_PCODE_READ_RC6VIDS		0x5

#define   GEN6_PCODE_READ_D_COMP		0x10

#define   GEN6_PCODE_WRITE_D_COMP		0x11

#define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)

#define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)

#define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)

#define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)

#define GEN6_PCODE_DATA				0x138128

#define GEN6_PCODE_DATA				0x138128

drivers/gpu/drm/i915/intel_display.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -6140,7 +6140,10 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 




	val = I915_READ(D_COMP);

	val = I915_READ(D_COMP);

	val |= D_COMP_COMP_DISABLE;

	val |= D_COMP_COMP_DISABLE;

	I915_WRITE(D_COMP, val);

	mutex_lock(&dev_priv->rps.hw_lock);

	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))

		DRM_ERROR("Failed to disable D_COMP\n");

	mutex_unlock(&dev_priv->rps.hw_lock);

	POSTING_READ(D_COMP);

	POSTING_READ(D_COMP);

	ndelay(100);

	ndelay(100);
@@ -6182,7 +6185,10 @@ void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 
	val = I915_READ(D_COMP);

	val = I915_READ(D_COMP);

	val |= D_COMP_COMP_FORCE;

	val |= D_COMP_COMP_FORCE;

	val &= ~D_COMP_COMP_DISABLE;

	val &= ~D_COMP_COMP_DISABLE;

	I915_WRITE(D_COMP, val);

	mutex_lock(&dev_priv->rps.hw_lock);

	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))

		DRM_ERROR("Failed to enable D_COMP\n");

	mutex_unlock(&dev_priv->rps.hw_lock);

	POSTING_READ(D_COMP);

	POSTING_READ(D_COMP);





	val = I915_READ(LCPLL_CTL);

	val = I915_READ(LCPLL_CTL);