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Commit 51511d05 authored by Thierry Reding's avatar Thierry Reding
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drm/tegra: sor: Write correct head state registers 



The head state registers are per head, so they must be properly indexed.
This has worked fine so far because all boards with eDP use it as the
primary output, so it is very likely to end up attached to head 0.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 80444495

drivers/gpu/drm/tegra/sor.c

+6 −4
Original line number Diff line number Diff line
@@ -1304,25 +1304,27 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder, 
	 */



	value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);

	tegra_sor_writel(sor, value, SOR_HEAD_STATE1(0));

	tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));



	vse = mode->vsync_end - mode->vsync_start - 1;

	hse = mode->hsync_end - mode->hsync_start - 1;



	value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);

	tegra_sor_writel(sor, value, SOR_HEAD_STATE2(0));

	tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));



	vbe = vse + (mode->vsync_start - mode->vdisplay);

	hbe = hse + (mode->hsync_start - mode->hdisplay);



	value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);

	tegra_sor_writel(sor, value, SOR_HEAD_STATE3(0));

	tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));



	vbs = vbe + mode->vdisplay;

	hbs = hbe + mode->hdisplay;



	value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);

	tegra_sor_writel(sor, value, SOR_HEAD_STATE4(0));

	tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));



	tegra_sor_writel(sor, 0x1, SOR_HEAD_STATE5(dc->pipe));



	/* CSTM (LVDS, link A/B, upper) */

	value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |