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Commit 50dfe70f authored by Anton Vorontsov's avatar Anton Vorontsov Committed by Linus Torvalds
Browse files

powerpc: introduce and document sdhci,wp-inverted property for eSDHC 



eSDHC block in MPC837x SOCs reports inverted write-protect state, soon
sdhci-of driver will look for sdhci,wp-inverted properties to decide
whether apply a specific quirk.

So, document the property and add it to device tree source files.

Signed-off-by: default avatarAnton Vorontsov <avorontsov@ru.mvista.com>
Cc: Pierre Ossman <pierre@ossman.eu>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: David Vrabel <david.vrabel@csr.com>
Cc: Ben Dooks <ben@fluff.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 81b39802

Documentation/powerpc/dts-bindings/fsl/esdhc.txt

+2 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ Required properties: 
  - interrupts : should contain eSDHC interrupt.

  - interrupt-parent : interrupt source phandle.

  - clock-frequency : specifies eSDHC base clock frequency.

  - sdhci,wp-inverted : (optional) specifies that eSDHC controller

    reports inverted write-protect state;

  - sdhci,1-bit-only : (optional) specifies that a controller can

    only handle 1-bit data transfers.

arch/powerpc/boot/dts/mpc8377_mds.dts

+1 −0
Original line number Diff line number Diff line
@@ -159,6 +159,7 @@ 
				reg = <0x2e000 0x1000>;

				interrupts = <42 0x8>;

				interrupt-parent = <&ipic>;

				sdhci,wp-inverted;

				/* Filled in by U-Boot */

				clock-frequency = <0>;

			};

arch/powerpc/boot/dts/mpc8377_rdb.dts

+1 −0
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ 
				reg = <0x2e000 0x1000>;

				interrupts = <42 0x8>;

				interrupt-parent = <&ipic>;

				sdhci,wp-inverted;

				/* Filled in by U-Boot */

				clock-frequency = <111111111>;

			};

arch/powerpc/boot/dts/mpc8377_wlan.dts

+1 −0
Original line number Diff line number Diff line
@@ -150,6 +150,7 @@ 
				reg = <0x2e000 0x1000>;

				interrupts = <42 0x8>;

				interrupt-parent = <&ipic>;

				sdhci,wp-inverted;

				clock-frequency = <133333333>;

			};

		};

arch/powerpc/boot/dts/mpc8378_mds.dts

+1 −0
Original line number Diff line number Diff line
@@ -159,6 +159,7 @@ 
				reg = <0x2e000 0x1000>;

				interrupts = <42 0x8>;

				interrupt-parent = <&ipic>;

				sdhci,wp-inverted;

				/* Filled in by U-Boot */

				clock-frequency = <0>;

			};