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Commit 5093eedc authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
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tg3: Apply 10Mbps fix to all 57765 revisions 



Commit a977dbe8, entitled
"tg3: Reduce 57765 core clock when link at 10Mbps" needs to be applied
to all revisions of the 57765 asic rev, not just the A0 revision.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2fe66ec2

drivers/net/tg3.c

+12 −9
Original line number Diff line number Diff line
@@ -7860,6 +7860,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		tw32(GRC_MODE, grc_mode);

	}



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {

		if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {

			u32 grc_mode = tr32(GRC_MODE);
@@ -7867,11 +7868,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
			val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;

			tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);



		val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);

			val = tr32(TG3_PCIE_TLDLPL_PORT +

				   TG3_PCIE_PL_LO_PHYCTL5);

			tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,

			     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);



			tw32(GRC_MODE, grc_mode);

		}



		val = tr32(TG3_CPMU_LSPD_10MB_CLK);

		val &= ~CPMU_LSPD_10MB_MACCLK_MASK;