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Commit 5081ce62 authored by Nishanth Menon's avatar Nishanth Menon Committed by Tony Lindgren
Browse files

ARM: dts: OMAP3+: Add PRM interrupt 



Provide OMAP3, 4 and OMAP5 with interrupt number for PRM

And for DRA7, provide crossbar number for prm interrupt.

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 01ac4565

arch/arm/boot/dts/dra7.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 
		prm: prm@4ae06000 {

			compatible = "ti,dra7-prm";

			reg = <0x4ae06000 0x3000>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;



			prm_clocks: clocks {

				#address-cells = <1>;

arch/arm/boot/dts/omap3.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ 
		prm: prm@48306000 {

			compatible = "ti,omap3-prm";

			reg = <0x48306000 0x4000>;

			interrupts = <11>;



			prm_clocks: clocks {

				#address-cells = <1>;

arch/arm/boot/dts/omap4.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -129,6 +129,7 @@ 
		prm: prm@4a306000 {

			compatible = "ti,omap4-prm";

			reg = <0x4a306000 0x3000>;

			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;



			prm_clocks: clocks {

				#address-cells = <1>;

arch/arm/boot/dts/omap5.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ 
		prm: prm@4ae06000 {

			compatible = "ti,omap5-prm";

			reg = <0x4ae06000 0x3000>;

			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;



			prm_clocks: clocks {

				#address-cells = <1>;