PCI: hisi: Add HiSilicon SoC Hip05 PCIe driver

		reboot-offset = <0x4>;

	};

-----------------------------------------------------------------------

Hisilicon HiP05 PCIe-SAS system controller

Required properties:

- compatible : "hisilicon,pcie-sas-subctrl", "syscon";

- reg : Register address and size

The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in

HiP05 Soc to implement some basic configurations.

Example:

	/* for HiP05 PCIe-SAS system */

	pcie_sas: system_controller@0xb0000000 {

		compatible = "hisilicon,pcie-sas-subctrl", "syscon";

		reg = <0xb0000000 0x10000>;

	};

-----------------------------------------------------------------------

Hisilicon CPU controller

HiSilicon PCIe host bridge DT description

HiSilicon PCIe host controller is based on Designware PCI core.

It shares common functions with PCIe Designware core driver and inherits

common properties defined in

Documentation/devicetree/bindings/pci/designware-pci.txt.

Additional properties are described here:

Required properties:

- compatible: Should contain "hisilicon,hip05-pcie".

- reg: Should contain rc_dbi, config registers location and length.

- reg-names: Must include the following entries:

  "rc_dbi": controller configuration registers;

  "config": PCIe configuration space registers.

- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.

- port-id: Should be 0, 1, 2 or 3.

Optional properties:

- status: Either "ok" or "disabled".

- dma-coherent: Present if DMA operations are coherent.

Example:

	pcie@0xb0080000 {

		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";

		reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;

		reg-names = "rc_dbi", "config";

		bus-range = <0  15>;

		msi-parent = <&its_pcie>;

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		dma-coherent;

		ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;

		num-lanes = <8>;

		port-id = <1>;

		#interrupts-cells = <1>;

		interrupts-map-mask = <0xf800 0 0 7>;

		interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10

				  0x0 0 0 2 &mbigen_pcie 2 11

				  0x0 0 0 3 &mbigen_pcie 3 12

				  0x0 0 0 4 &mbigen_pcie 4 13>;

		status = "ok";

	};

F:	Documentation/devicetree/bindings/pci/xgene-pci-msi.txt

F:	drivers/pci/host/pci-xgene-msi.c

PCIE DRIVER FOR HISILICON

M:	Zhou Wang <wangzhou1@hisilicon.com>

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/hisilicon-pcie.txt

F:	drivers/pci/host/pcie-hisi.c

PCMCIA SUBSYSTEM

P:	Linux PCMCIA Team

L:	linux-pcmcia@lists.infradead.org

	  Say Y here if you want to use the Broadcom iProc PCIe controller

	  through the BCMA bus interface

config PCI_HISI

	depends on OF && ARM64

	bool "HiSilicon SoC HIP05 PCIe controller"

	select PCIEPORTBUS

	select PCIE_DW

	help

	  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC

endmenu

obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o

obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o

obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o

obj-$(CONFIG_PCI_HISI) += pcie-hisi.o