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Commit 50095647 authored by Sayali Lokhande's avatar Sayali Lokhande
Browse files

ARM: dts: msm: Enable sdhc1 and sdhc2 for msm8937 



Add DT entries to support eMMC and SD card in msm8937
platform.

Change-Id: I2e34f0aaa67545d3eade196c122ab4587ecac822
Signed-off-by: default avatarSayali Lokhande <sayalil@codeaurora.org>
parent 98cddae6

arch/arm64/boot/dts/qcom/msm8937-mtp.dtsi

+49 −0
Original line number Diff line number Diff line
@@ -14,3 +14,52 @@ 
&blsp1_uart2 {

	status = "ok";

};



&sdhc_1 {

	/* device core power supply */

	vdd-supply = <&pm8937_l8>;

	qcom,vdd-voltage-level = <2900000 2900000>;

	qcom,vdd-current-level = <200 570000>;



	/* device communication power supply */

	vdd-io-supply = <&pm8937_l5>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <200 325000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000

								384000000>;

	qcom,nonremovable;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";



	status = "ok";

};



&sdhc_2 {

	/* device core power supply */

	vdd-supply = <&pm8937_l11>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <15000 800000>;



	/* device communication power supply */

	vdd-io-supply = <&pm8937_l12>;

	qcom,vdd-io-voltage-level = <1800000 2950000>;

	qcom,vdd-io-current-level = <200 22000>;



	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;

	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;



	cd-gpios = <&tlmm 67 0x1>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000

								200000000>;

	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";



	status = "ok";

};

arch/arm64/boot/dts/qcom/msm8937.dtsi

+111 −0
Original line number Diff line number Diff line
@@ -109,6 +109,8 @@ 
		i2c5 = &i2c_5;

		spi3 = &spi_3;

		i2c3 = &i2c_3;

		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */

		sdhc2 = &sdhc_2; /* SDC2 for SD card */

	};



	soc: soc { };
@@ -1158,6 +1160,115 @@ 
		memory-region = <&adsp_mem>;

	};



	sdcc1_ice: sdcc1ice@7803000 {

		compatible = "qcom,ice";

		reg = <0x7803000 0x8000>;

		interrupt-names = "sdcc_ice_nonsec_level_irq",

				  "sdcc_ice_sec_level_irq";

		interrupts = <0 312 0>, <0 313 0>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>,

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>,

			 <&clock_gcc clk_gcc_sdcc1_ahb_clk>;

		qcom,op-freq-hz = <200000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<78 512 0 0>,    /* No vote */

			<78 512 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN", "MAX";

		qcom,instance-type = "sdcc";

	};



	sdhc_1: sdhci@7824900 {

		compatible = "qcom,sdhci-msm";

		reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>;

		reg-names = "hc_mem", "core_mem", "cmdq_mem";



		interrupts = <0 123 0>, <0 138 0>;

		interrupt-names = "hc_irq", "pwr_irq";



		sdhc-msm-crypto = <&sdcc1_ice>;

		qcom,bus-width = <8>;

		qcom,large-address-bus;



		qcom,devfreq,freq-table = <50000000 200000000>;



		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <2 200>;



		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cmdq-latency-us = <2 200>, <2 200>;



		qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;



		qcom,msm-bus,name = "sdhc1";

		qcom,msm-bus,num-cases = <9>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */

			<78 512 1046 3200>,    /* 400 KB/s*/

			<78 512 52286 160000>, /* 20 MB/s */

			<78 512 65360 200000>, /* 25 MB/s */

			<78 512 130718 400000>, /* 50 MB/s */

			<78 512 130718 400000>, /* 100 MB/s */

			<78 512 261438 800000>, /* 200 MB/s */

			<78 512 261438 800000>, /* 400 MB/s */

			<78 512 1338562 4096000>; /* Max. bandwidth */

		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000

			50000000 100000000 200000000 400000000 4294967295>;



		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>,

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>;

		clock-names = "iface_clk", "core_clk", "ice_core_clk";

		qcom,ice-clk-rates = <200000000 100000000>;



		qcom,scaling-lower-bus-speed-mode = "DDR52";

		status = "disabled";

	};



	sdhc_2: sdhci@7864900 {

		compatible = "qcom,sdhci-msm";

		reg = <0x7864900 0x500>, <0x7864000 0x800>;

		reg-names = "hc_mem", "core_mem";



		interrupts = <0 125 0>, <0 221 0>;

		interrupt-names = "hc_irq", "pwr_irq";



		qcom,bus-width = <4>;

		qcom,large-address-bus;



		qcom,pm-qos-irq-type = "affine_irq";

		qcom,pm-qos-irq-latency = <2 200>;



		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;



		qcom,msm-bus,name = "sdhc2";

		qcom,msm-bus,num-cases = <8>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */

			<81 512 1046 3200>,    /* 400 KB/s*/

			<81 512 52286 160000>, /* 20 MB/s */

			<81 512 65360 200000>, /* 25 MB/s */

			<81 512 130718 400000>, /* 50 MB/s */

			<81 512 261438 800000>, /* 100 MB/s */

			<81 512 261438 800000>, /* 200 MB/s */

			<81 512 1338562 4096000>; /* Max. bandwidth */

		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000

			100000000 200000000 4294967295>;



		qcom,devfreq,freq-table = <50000000 200000000>;

		clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,

			<&clock_gcc clk_gcc_sdcc2_apps_clk>;

		clock-names = "iface_clk", "core_clk";



		status = "disabled";

	};

};



#include "pm8937-rpm-regulator.dtsi"