Merge 5ce50ccf on remote branch

					--> Sleep value (in ms)

- qcom,partial-update-enabled:		Boolean used to enable partial

					panel update for command mode panels.

- qcom,partial-update-addr-offset:	An array of two values indicate the panel

					column, row address offset value.

					Two default values are 0.

- qcom,mdss-dsi-horizontal-line-idle:	List of width ranges (EC - SC) in pixels indicating

					additional idle time in dsi clock cycles that is needed

					to compensate for smaller line width.

	compress: qcom,msm-compress-dsp {

		compatible = "qcom,msm-compress-dsp";

		qcom,adsp-version = "MDSP 1.2";

		qcom,adsp-version = "MDSP 2.8";

	};

	qcom,msm-dai-stub {

		qcom,mdss-dsi-pixel-packing = "tight";

		qcom,mdss-dsi-pixel-alignment = <0>;

		qcom,mdss-dsi-on-command = [

			15 01 00 00 00 00 02 FE 01

			15 01 00 00 00 00 02 6A 03

			15 01 00 00 00 00 02 FE 00

			15 01 00 00 00 00 02 35 00

			15 01 00 00 00 00 02 53 20

			15 01 00 00 00 00 02 51 80

			39 01 00 00 00 00 05 2A 00 10 01 7F

			39 01 00 00 00 00 05 2B 00 00 01 BF

			05 01 00 00 00 00 01 39   /* Idle-Mode On */

			];

		qcom,mdss-dsi-idle-off-command = [

			15 01 00 00 00 00 02 FE 00

			15 01 00 00 00 00 02 53 20

			05 01 00 00 00 00 01 38   /* Idle-Mode Off */

			];

		qcom,mdss-dsi-idle-on-command-state = "dsi_hs_mode";

	/delete-property/ qcom,mdss-dsi-panel-timings;

	qcom,mdss-dsi-panel-timings-phy-12nm = [04 04 01 08 00 03 01 0D];

	qcom,panel-supply-entries = <&dsi_pm660_panel_pwr_supply>;

	qcom,partial-update-enabled;

	qcom,partial-update-addr-offset = <0x10 0>;

	qcom,panel-roi-alignment = <2 2 4 2 20 2>;

	qcom,esd-check-enabled;

	qcom,mdss-dsi-panel-status-check-mode = "te_signal_check";

};

/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

		PAGE_SIZE, 0, KGSL_MEMDESC_PRIVILEGED, "pagetable_desc");

	if (ret)

		return ret;

	/* allocate a chunk of memory to create user profiling IB1s */

	kgsl_allocate_global(KGSL_DEVICE(adreno_dev), &rb->profile_desc,

		PAGE_SIZE, KGSL_MEMFLAGS_GPUREADONLY, 0, "profile_desc");

	return kgsl_allocate_global(KGSL_DEVICE(adreno_dev), &rb->buffer_desc,

			KGSL_RB_SIZE, KGSL_MEMFLAGS_GPUREADONLY,

			0, "ringbuffer");

	if (!adreno_is_a3xx(adreno_dev)) {

		status = kgsl_allocate_global(device, &device->scratch,

				PAGE_SIZE, 0, 0, "scratch");

				PAGE_SIZE, 0, KGSL_MEMDESC_RANDOM, "scratch");

		if (status != 0)

			return status;

	}

	kgsl_free_global(device, &rb->pagetable_desc);

	kgsl_free_global(device, &rb->preemption_desc);

	kgsl_free_global(device, &rb->profile_desc);

	kgsl_free_global(device, &rb->buffer_desc);

	kgsl_del_event_group(&rb->events);

	memset(rb, 0, sizeof(struct adreno_ringbuffer));

	return (unsigned int)(p - cmds);

}

/* This is the maximum possible size for 64 bit targets */

#define PROFILE_IB_DWORDS 4

#define PROFILE_IB_SLOTS (PAGE_SIZE / (PROFILE_IB_DWORDS << 2))

static int set_user_profiling(struct adreno_device *adreno_dev,

		struct adreno_ringbuffer *rb, u32 *cmds, u64 gpuaddr)

{

	int dwords, index = 0;

	u64 ib_gpuaddr;

	u32 *ib;

	if (!rb->profile_desc.hostptr)

		return 0;

	ib = ((u32 *) rb->profile_desc.hostptr) +

		(rb->profile_index * PROFILE_IB_DWORDS);

	ib_gpuaddr = rb->profile_desc.gpuaddr +

		(rb->profile_index * (PROFILE_IB_DWORDS << 2));

	dwords = _get_alwayson_counter(adreno_dev, ib, gpuaddr);

	/* Make an indirect buffer for the request */

	cmds[index++] = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1);

	index += cp_gpuaddr(adreno_dev, &cmds[index], ib_gpuaddr);

	cmds[index++] = dwords;

	rb->profile_index = (rb->profile_index + 1) % PROFILE_IB_SLOTS;

	return index;

}

/* adreno_rindbuffer_submitcmd - submit userspace IBs to the GPU */

int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev,

		struct kgsl_drawobj_cmd *cmdobj,

		!adreno_is_a3xx(adreno_dev) &&

		(cmdobj->profiling_buf_entry != NULL)) {

		user_profiling = true;

		dwords += 6;

		/*

		 * REG_TO_MEM packet on A5xx and above needs another ordinal.

		 * Add 2 more dwords since we do profiling before and after.

		 * User side profiling uses two IB1s, one before with 4 dwords

		 * per INDIRECT_BUFFER_PFE call

		 */

		if (!ADRENO_LEGACY_PM4(adreno_dev))

			dwords += 2;

		dwords += 8;

		/*

		 * we want to use an adreno_submit_time struct to get the

	}

	/*

	 * Add cmds to read the GPU ticks at the start of command obj and

	 * Add IB1 to read the GPU ticks at the start of command obj and

	 * write it into the appropriate command obj profiling buffer offset

	 */

	if (user_profiling) {

		cmds += _get_alwayson_counter(adreno_dev, cmds,

		cmds += set_user_profiling(adreno_dev, rb, cmds,

			cmdobj->profiling_buffer_gpuaddr +

			offsetof(struct kgsl_drawobj_profiling_buffer,

			gpu_ticks_submitted));

	}

	/*

	 * Add cmds to read the GPU ticks at the end of command obj and

	 * Add IB1 to read the GPU ticks at the end of command obj and

	 * write it into the appropriate command obj profiling buffer offset

	 */

	if (user_profiling) {

		cmds += _get_alwayson_counter(adreno_dev, cmds,

		cmds += set_user_profiling(adreno_dev, rb, cmds,

			cmdobj->profiling_buffer_gpuaddr +

			offsetof(struct kgsl_drawobj_profiling_buffer,

			gpu_ticks_retired));