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Commit 4ee2ea5b authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "iommu: arm-smmu: Add configuration option for page table levels" into msm-4.9

parents e2918217 4423d3e7

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+5 −0
Original line number Diff line number Diff line
@@ -86,6 +86,11 @@ conditions. 
		  useful if the upstream hardware is capable of switching

		  between multiple domains within a single context bank.



- qcom,use-3-lvl-tables:

		  Some hardware configurations may not be optimized for using

		  a four level page table configuration. Set to use a three

		  level page table instead.



- clocks        : List of clocks to be used during SMMU register access. See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for information about the format. For each clock specified

drivers/iommu/arm-smmu.c

+4 −0
Original line number Diff line number Diff line
@@ -411,6 +411,7 @@ struct arm_smmu_device { 
#define ARM_SMMU_OPT_FATAL_ASF		(1 << 1)

#define ARM_SMMU_OPT_SKIP_INIT		(1 << 2)

#define ARM_SMMU_OPT_DYNAMIC		(1 << 3)

#define ARM_SMMU_OPT_3LVL_TABLES	(1 << 4)

	u32				options;

	enum arm_smmu_arch_version	version;

	enum arm_smmu_implementation	model;
@@ -529,6 +530,7 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { 
	{ ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" },

	{ ARM_SMMU_OPT_SKIP_INIT, "qcom,skip-init" },

	{ ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" },

	{ ARM_SMMU_OPT_3LVL_TABLES, "qcom,use-3-lvl-tables" },

	{ 0, NULL},

};
@@ -1567,6 +1569,8 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, 
		oas = smmu->ipa_size;

		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {

			fmt = ARM_64_LPAE_S1;

			if (smmu->options & ARM_SMMU_OPT_3LVL_TABLES)

				ias = min(ias, 39UL);

		} else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) {

			fmt = ARM_32_LPAE_S1;

			ias = min(ias, 32UL);