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Commit 4ea68128 authored by Tarun Karra's avatar Tarun Karra
Browse files

msm: kgsl: Add IFPC static registers to powerup register list 



Add IFPC static registers to powerup register list. These are
restored by CP after IFPC.

Change-Id: I0e3e01d4bfee57fcfebb74be6a5237f0c79fba30
Signed-off-by: default avatarTarun Karra <tkarra@codeaurora.org>
parent a6674362

drivers/gpu/msm/a6xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ 
#define A6XX_CP_MEM_POOL_SIZE            0x8C3

#define A6XX_CP_CHICKEN_DBG              0x841

#define A6XX_CP_ADDR_MODE_CNTL           0x842

#define A6XX_CP_DBG_ECO_CNTL             0x843

#define A6XX_CP_PROTECT_CNTL             0x84F

#define A6XX_CP_PROTECT_REG              0x850

#define A6XX_CP_CONTEXT_SWITCH_CNTL      0x8A0

drivers/gpu/msm/adreno_a6xx.c

+60 −8
Original line number Diff line number Diff line
@@ -281,6 +281,7 @@ static struct a6xx_protected_regs { 
	{ 0xA630, 0x0, 1 },

};



/* IFPC & Preemption static powerup restore list */

static struct reg_list_pair {

	uint32_t offset;

	uint32_t val;
@@ -315,6 +316,48 @@ static struct reg_list_pair { 
	{ A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x0 },

};



/* IFPC only static powerup restore list */

static struct reg_list_pair a6xx_ifpc_pwrup_reglist[] = {

	{ A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x0 },

	{ A6XX_CP_CHICKEN_DBG, 0x0 },

	{ A6XX_CP_ADDR_MODE_CNTL, 0x0 },

	{ A6XX_CP_DBG_ECO_CNTL, 0x0 },

	{ A6XX_CP_PROTECT_CNTL, 0x0 },

	{ A6XX_CP_PROTECT_REG, 0x0 },

	{ A6XX_CP_PROTECT_REG+1, 0x0 },

	{ A6XX_CP_PROTECT_REG+2, 0x0 },

	{ A6XX_CP_PROTECT_REG+3, 0x0 },

	{ A6XX_CP_PROTECT_REG+4, 0x0 },

	{ A6XX_CP_PROTECT_REG+5, 0x0 },

	{ A6XX_CP_PROTECT_REG+6, 0x0 },

	{ A6XX_CP_PROTECT_REG+7, 0x0 },

	{ A6XX_CP_PROTECT_REG+8, 0x0 },

	{ A6XX_CP_PROTECT_REG+9, 0x0 },

	{ A6XX_CP_PROTECT_REG+10, 0x0 },

	{ A6XX_CP_PROTECT_REG+11, 0x0 },

	{ A6XX_CP_PROTECT_REG+12, 0x0 },

	{ A6XX_CP_PROTECT_REG+13, 0x0 },

	{ A6XX_CP_PROTECT_REG+14, 0x0 },

	{ A6XX_CP_PROTECT_REG+15, 0x0 },

	{ A6XX_CP_PROTECT_REG+16, 0x0 },

	{ A6XX_CP_PROTECT_REG+17, 0x0 },

	{ A6XX_CP_PROTECT_REG+18, 0x0 },

	{ A6XX_CP_PROTECT_REG+19, 0x0 },

	{ A6XX_CP_PROTECT_REG+20, 0x0 },

	{ A6XX_CP_PROTECT_REG+21, 0x0 },

	{ A6XX_CP_PROTECT_REG+22, 0x0 },

	{ A6XX_CP_PROTECT_REG+23, 0x0 },

	{ A6XX_CP_PROTECT_REG+24, 0x0 },

	{ A6XX_CP_PROTECT_REG+25, 0x0 },

	{ A6XX_CP_PROTECT_REG+26, 0x0 },

	{ A6XX_CP_PROTECT_REG+27, 0x0 },

	{ A6XX_CP_PROTECT_REG+28, 0x0 },

	{ A6XX_CP_PROTECT_REG+29, 0x0 },

	{ A6XX_CP_PROTECT_REG+30, 0x0 },

	{ A6XX_CP_PROTECT_REG+31, 0x0 },

	{ A6XX_CP_AHB_CNTL, 0x0 },

};



static void _update_always_on_regs(struct adreno_device *adreno_dev)

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
@@ -501,11 +544,16 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
{

	uint32_t i;

	struct cpu_gpu_lock *lock;

	struct reg_list_pair *r;



	/* Set up the register values */

	for (i = 0; i < ARRAY_SIZE(a6xx_pwrup_reglist); i++) {

		struct reg_list_pair *r = &a6xx_pwrup_reglist[i];

	for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_pwrup_reglist); i++) {

		r = &a6xx_ifpc_pwrup_reglist[i];

		kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val);

	}



	for (i = 0; i < ARRAY_SIZE(a6xx_pwrup_reglist); i++) {

		r = &a6xx_pwrup_reglist[i];

		kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val);

	}
@@ -526,11 +574,14 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) 
	 * empty). And list_offset should be specified as the size in dwords

	 * of the static IFPC-only register list.

	 */

	lock->list_length = sizeof(a6xx_pwrup_reglist) >> 2;

	lock->list_offset = 0;



	memcpy(adreno_dev->pwrup_reglist.hostptr +

		sizeof(*lock),

	lock->list_length = (sizeof(a6xx_ifpc_pwrup_reglist) +

			sizeof(a6xx_pwrup_reglist)) >> 2;

	lock->list_offset = sizeof(a6xx_ifpc_pwrup_reglist) >> 2;



	memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock),

		a6xx_ifpc_pwrup_reglist, sizeof(a6xx_ifpc_pwrup_reglist));

	memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock)

		+ sizeof(a6xx_ifpc_pwrup_reglist),

		a6xx_pwrup_reglist, sizeof(a6xx_pwrup_reglist));

}
@@ -796,7 +847,8 @@ static void _set_ordinals(struct adreno_device *adreno_dev, 
		*cmds++ = lower_32_bits(gpuaddr);

		*cmds++ = upper_32_bits(gpuaddr);

		/* Size is in dwords */

		*cmds++ = sizeof(a6xx_pwrup_reglist) >> 2;

		*cmds++ = (sizeof(a6xx_ifpc_pwrup_reglist) +

			sizeof(a6xx_pwrup_reglist)) >> 2;

	}



	/* Pad rest of the cmds with 0's */