drm/nouveau: move engine object creation into per-engine hooks (4ea52f89) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/nouveau/nouveau_drv.h

+7 −0

drivers/gpu/drm/nouveau/nouveau_object.c

+13 −82

Original line number	Original line	Diff line number	Diff line
	@@ -361,20 +361,6 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
	return 0;		return 0;
	}		}


	static uint32_t
	nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
	{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/XXX: dodgy hack for now /
	if (dev_priv->card_type >= NV_50)
	return 24;
	if (dev_priv->card_type >= NV_40)
	return 32;
	return 16;
	}

	/*		/*
	DMA objects are used to reference a piece of memory in the		DMA objects are used to reference a piece of memory in the
	framebuffer, PCI or AGP address space. Each object is 16 bytes big		framebuffer, PCI or AGP address space. Each object is 16 bytes big
	@@ -606,11 +592,11 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
	set to 0?		set to 0?
	*/		*/
	static int		static int
	nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,		nouveau_gpuobj_sw_new(struct nouveau_channel *chan, u32 handle, u16 class)
	struct nouveau_gpuobj **gpuobj_ret)
	{		{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;		struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct nouveau_gpuobj *gpuobj;		struct nouveau_gpuobj *gpuobj;
			int ret;

	gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);		gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
	if (!gpuobj)		if (!gpuobj)
	@@ -624,17 +610,20 @@ nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
	spin_lock(&dev_priv->ramin_lock);		spin_lock(&dev_priv->ramin_lock);
	list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);		list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
	spin_unlock(&dev_priv->ramin_lock);		spin_unlock(&dev_priv->ramin_lock);
	*gpuobj_ret = gpuobj;
	return 0;		ret = nouveau_ramht_insert(chan, handle, gpuobj);
			nouveau_gpuobj_ref(NULL, &gpuobj);
			return ret;
	}		}

	int		int
	nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)		nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
	{		{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;		struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
			struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
			struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
	struct drm_device *dev = chan->dev;		struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj_class *oc;		struct nouveau_gpuobj_class *oc;
	struct nouveau_gpuobj *gpuobj;
	int ret;		int ret;

	NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);		NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
	@@ -650,85 +639,27 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
	found:		found:
	switch (oc->engine) {		switch (oc->engine) {
	case NVOBJ_ENGINE_SW:		case NVOBJ_ENGINE_SW:
	if (dev_priv->card_type < NV_C0) {		return nouveau_gpuobj_sw_new(chan, handle, class);
	ret = nouveau_gpuobj_sw_new(chan, class, &gpuobj);
	if (ret)
	return ret;
	goto insert;
	}
	break;
	case NVOBJ_ENGINE_GR:		case NVOBJ_ENGINE_GR:
	if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) \|\|		if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) \|\|
	(dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) {		(dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) {
	struct nouveau_pgraph_engine *pgraph =
	&dev_priv->engine.graph;

	ret = pgraph->create_context(chan);		ret = pgraph->create_context(chan);
	if (ret)		if (ret)
	return ret;		return ret;
	}		}
	break;
			return pgraph->object_new(chan, handle, class);
	case NVOBJ_ENGINE_CRYPT:		case NVOBJ_ENGINE_CRYPT:
	if (!chan->crypt_ctx) {		if (!chan->crypt_ctx) {
	struct nouveau_crypt_engine *pcrypt =
	&dev_priv->engine.crypt;

	ret = pcrypt->create_context(chan);		ret = pcrypt->create_context(chan);
	if (ret)		if (ret)
	return ret;		return ret;
	}		}
	break;
	}

	/* we're done if this is fermi */		return pcrypt->object_new(chan, handle, class);
	if (dev_priv->card_type >= NV_C0)
	return 0;

	ret = nouveau_gpuobj_new(dev, chan,
	nouveau_gpuobj_class_instmem_size(dev, class),
	16,
	NVOBJ_FLAG_ZERO_ALLOC \| NVOBJ_FLAG_ZERO_FREE,
	&gpuobj);
	if (ret) {
	NV_ERROR(dev, "error creating gpuobj: %d\n", ret);
	return ret;
	}

	if (dev_priv->card_type >= NV_50) {
	nv_wo32(gpuobj, 0, class);
	nv_wo32(gpuobj, 20, 0x00010000);
	} else {
	switch (class) {
	case NV_CLASS_NULL:
	nv_wo32(gpuobj, 0, 0x00001030);
	nv_wo32(gpuobj, 4, 0xFFFFFFFF);
	break;
	default:
	if (dev_priv->card_type >= NV_40) {
	nv_wo32(gpuobj, 0, class);
	#ifdef __BIG_ENDIAN
	nv_wo32(gpuobj, 8, 0x01000000);
	#endif
	} else {
	#ifdef __BIG_ENDIAN
	nv_wo32(gpuobj, 0, class \| 0x00080000);
	#else
	nv_wo32(gpuobj, 0, class);
	#endif
	}		}
	}
	}
	dev_priv->engine.instmem.flush(dev);

	gpuobj->engine = oc->engine;		BUG_ON(1);
	gpuobj->class = oc->id;

	insert:
	ret = nouveau_ramht_insert(chan, handle, gpuobj);
	if (ret)
	NV_ERROR(dev, "error adding gpuobj to RAMHT: %d\n", ret);
	nouveau_gpuobj_ref(NULL, &gpuobj);
	return ret;
	}		}

	static int		static int

drivers/gpu/drm/nouveau/nouveau_state.c

+8 −0

drivers/gpu/drm/nouveau/nv04_graph.c

+28 −0

Original line number	Original line	Diff line number	Diff line
	@@ -28,6 +28,7 @@
	#include "nouveau_drv.h"		#include "nouveau_drv.h"
	#include "nouveau_hw.h"		#include "nouveau_hw.h"
	#include "nouveau_util.h"		#include "nouveau_util.h"
			#include "nouveau_ramht.h"

	static int nv04_graph_register(struct drm_device *dev);		static int nv04_graph_register(struct drm_device *dev);
	static void nv04_graph_isr(struct drm_device *dev);		static void nv04_graph_isr(struct drm_device *dev);
	@@ -481,6 +482,33 @@ nv04_graph_unload_context(struct drm_device *dev)
	return 0;		return 0;
	}		}

			int
			nv04_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
			{
			struct drm_device *dev = chan->dev;
			struct nouveau_gpuobj *obj = NULL;
			int ret;

			ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
			if (ret)
			return ret;
			obj->engine = 1;
			obj->class = class;

			#ifdef __BIG_ENDIAN
			nv_wo32(obj, 0x00, 0x00080000 \| class);
			#else
			nv_wo32(obj, 0x00, class);
			#endif
			nv_wo32(obj, 0x04, 0x00000000);
			nv_wo32(obj, 0x08, 0x00000000);
			nv_wo32(obj, 0x0c, 0x00000000);

			ret = nouveau_ramht_insert(chan, handle, obj);
			nouveau_gpuobj_ref(NULL, &obj);
			return ret;
			}

	int nv04_graph_init(struct drm_device *dev)		int nv04_graph_init(struct drm_device *dev)
	{		{
	struct drm_nouveau_private *dev_priv = dev->dev_private;		struct drm_nouveau_private *dev_priv = dev->dev_private;

drivers/gpu/drm/nouveau/nv40_graph.c

+27 −0

Original line number	Original line	Diff line number	Diff line
	@@ -28,6 +28,7 @@
	#include "drm.h"		#include "drm.h"
	#include "nouveau_drv.h"		#include "nouveau_drv.h"
	#include "nouveau_grctx.h"		#include "nouveau_grctx.h"
			#include "nouveau_ramht.h"

	static int nv40_graph_register(struct drm_device *);		static int nv40_graph_register(struct drm_device *);
	static void nv40_graph_isr(struct drm_device *);		static void nv40_graph_isr(struct drm_device *);
	@@ -204,6 +205,32 @@ nv40_graph_unload_context(struct drm_device *dev)
	return ret;		return ret;
	}		}

			int
			nv40_graph_object_new(struct nouveau_channel *chan, u32 handle, u16 class)
			{
			struct drm_device *dev = chan->dev;
			struct nouveau_gpuobj *obj = NULL;
			int ret;

			ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
			if (ret)
			return ret;
			obj->engine = 1;
			obj->class = class;

			nv_wo32(obj, 0x00, class);
			nv_wo32(obj, 0x04, 0x00000000);
			#ifdef __BIG_ENDIAN
			nv_wo32(obj, 0x08, 0x01000000);
			#endif
			nv_wo32(obj, 0x0c, 0x00000000);
			nv_wo32(obj, 0x10, 0x00000000);

			ret = nouveau_ramht_insert(chan, handle, obj);
			nouveau_gpuobj_ref(NULL, &obj);
			return ret;
			}

	void		void
	nv40_graph_set_tile_region(struct drm_device *dev, int i)		nv40_graph_set_tile_region(struct drm_device *dev, int i)
	{		{

Original line number	Original line	Diff line number	Diff line
	@@ -73,6 +73,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
	engine->graph.destroy_context = nv04_graph_destroy_context;		engine->graph.destroy_context = nv04_graph_destroy_context;
	engine->graph.load_context = nv04_graph_load_context;		engine->graph.load_context = nv04_graph_load_context;
	engine->graph.unload_context = nv04_graph_unload_context;		engine->graph.unload_context = nv04_graph_unload_context;
			engine->graph.object_new = nv04_graph_object_new;
	engine->fifo.channels = 16;		engine->fifo.channels = 16;
	engine->fifo.init = nv04_fifo_init;		engine->fifo.init = nv04_fifo_init;
	engine->fifo.takedown = nv04_fifo_fini;		engine->fifo.takedown = nv04_fifo_fini;
	@@ -131,6 +132,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
	engine->graph.fifo_access = nv04_graph_fifo_access;		engine->graph.fifo_access = nv04_graph_fifo_access;
	engine->graph.load_context = nv10_graph_load_context;		engine->graph.load_context = nv10_graph_load_context;
	engine->graph.unload_context = nv10_graph_unload_context;		engine->graph.unload_context = nv10_graph_unload_context;
			engine->graph.object_new = nv04_graph_object_new;
	engine->graph.set_tile_region = nv10_graph_set_tile_region;		engine->graph.set_tile_region = nv10_graph_set_tile_region;
	engine->fifo.channels = 32;		engine->fifo.channels = 32;
	engine->fifo.init = nv10_fifo_init;		engine->fifo.init = nv10_fifo_init;
	@@ -190,6 +192,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
	engine->graph.fifo_access = nv04_graph_fifo_access;		engine->graph.fifo_access = nv04_graph_fifo_access;
	engine->graph.load_context = nv20_graph_load_context;		engine->graph.load_context = nv20_graph_load_context;
	engine->graph.unload_context = nv20_graph_unload_context;		engine->graph.unload_context = nv20_graph_unload_context;
			engine->graph.object_new = nv04_graph_object_new;
	engine->graph.set_tile_region = nv20_graph_set_tile_region;		engine->graph.set_tile_region = nv20_graph_set_tile_region;
	engine->fifo.channels = 32;		engine->fifo.channels = 32;
	engine->fifo.init = nv10_fifo_init;		engine->fifo.init = nv10_fifo_init;
	@@ -249,6 +252,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
	engine->graph.destroy_context = nv20_graph_destroy_context;		engine->graph.destroy_context = nv20_graph_destroy_context;
	engine->graph.load_context = nv20_graph_load_context;		engine->graph.load_context = nv20_graph_load_context;
	engine->graph.unload_context = nv20_graph_unload_context;		engine->graph.unload_context = nv20_graph_unload_context;
			engine->graph.object_new = nv04_graph_object_new;
	engine->graph.set_tile_region = nv20_graph_set_tile_region;		engine->graph.set_tile_region = nv20_graph_set_tile_region;
	engine->fifo.channels = 32;		engine->fifo.channels = 32;
	engine->fifo.init = nv10_fifo_init;		engine->fifo.init = nv10_fifo_init;
	@@ -311,6 +315,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
	engine->graph.destroy_context = nv40_graph_destroy_context;		engine->graph.destroy_context = nv40_graph_destroy_context;
	engine->graph.load_context = nv40_graph_load_context;		engine->graph.load_context = nv40_graph_load_context;
	engine->graph.unload_context = nv40_graph_unload_context;		engine->graph.unload_context = nv40_graph_unload_context;
			engine->graph.object_new = nv40_graph_object_new;
	engine->graph.set_tile_region = nv40_graph_set_tile_region;		engine->graph.set_tile_region = nv40_graph_set_tile_region;
	engine->fifo.channels = 32;		engine->fifo.channels = 32;
	engine->fifo.init = nv40_fifo_init;		engine->fifo.init = nv40_fifo_init;