Loading arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ arm,sg-enable; coresight-name = "coresight-tmc-etr"; coresight-csr = <&csr>; coresight-ctis = <&cti0 &cti8>; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -49,6 +50,7 @@ reg-names = "tmc-base"; coresight-name = "coresight-tmc-etf"; coresight-csr = <&csr>; arm,default-sink; coresight-ctis = <&cti0 &cti8>; Loading Loading @@ -1139,6 +1141,10 @@ reg-names = "csr-base"; coresight-name = "coresight-csr"; qcom,usb-bam-support; qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <1>; clocks = <&clock_gcc clk_qdss_clk>, Loading Loading @@ -1240,6 +1246,7 @@ "usbbam-mux", "blsp-mux"; coresight-name = "coresight-hwevent"; coresight-csr = <&csr>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading Loading
arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ arm,sg-enable; coresight-name = "coresight-tmc-etr"; coresight-csr = <&csr>; coresight-ctis = <&cti0 &cti8>; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -49,6 +50,7 @@ reg-names = "tmc-base"; coresight-name = "coresight-tmc-etf"; coresight-csr = <&csr>; arm,default-sink; coresight-ctis = <&cti0 &cti8>; Loading Loading @@ -1139,6 +1141,10 @@ reg-names = "csr-base"; coresight-name = "coresight-csr"; qcom,usb-bam-support; qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <1>; clocks = <&clock_gcc clk_qdss_clk>, Loading Loading @@ -1240,6 +1246,7 @@ "usbbam-mux", "blsp-mux"; coresight-name = "coresight-hwevent"; coresight-csr = <&csr>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading