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Commit 4db9a82f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2015-07-23' of git://anongit.freedesktop.org/drm-intel into drm-fixes 

arb_timer kernel side fix from Chris.

* tag 'drm-intel-fixes-2015-07-23' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: Use two 32bit reads for select 64bit REG_READ ioctls
parents 762043aa 648a9bc5

drivers/gpu/drm/i915/intel_uncore.c

+19 −7
Original line number Diff line number Diff line
@@ -1274,10 +1274,12 @@ int i915_reg_read_ioctl(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_reg_read *reg = data;

	struct register_whitelist const *entry = whitelist;

	unsigned size;

	u64 offset;

	int i, ret = 0;



	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {

		if (entry->offset == reg->offset &&

		if (entry->offset == (reg->offset & -entry->size) &&

		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))

			break;

	}
@@ -1285,23 +1287,33 @@ int i915_reg_read_ioctl(struct drm_device *dev, 
	if (i == ARRAY_SIZE(whitelist))

		return -EINVAL;



	/* We use the low bits to encode extra flags as the register should

	 * be naturally aligned (and those that are not so aligned merely

	 * limit the available flags for that register).

	 */

	offset = entry->offset;

	size = entry->size;

	size |= reg->offset ^ offset;



	intel_runtime_pm_get(dev_priv);



	switch (entry->size) {

	switch (size) {

	case 8 | 1:

		reg->val = I915_READ64_2x32(offset, offset+4);

		break;

	case 8:

		reg->val = I915_READ64(reg->offset);

		reg->val = I915_READ64(offset);

		break;

	case 4:

		reg->val = I915_READ(reg->offset);

		reg->val = I915_READ(offset);

		break;

	case 2:

		reg->val = I915_READ16(reg->offset);

		reg->val = I915_READ16(offset);

		break;

	case 1:

		reg->val = I915_READ8(reg->offset);

		reg->val = I915_READ8(offset);

		break;

	default:

		MISSING_CASE(entry->size);

		ret = -EINVAL;

		goto out;

	}

include/uapi/drm/i915_drm.h

+8 −0
Original line number Diff line number Diff line
@@ -1070,6 +1070,14 @@ struct drm_i915_reg_read { 
	__u64 offset;

	__u64 val; /* Return value */

};

/* Known registers:

 *

 * Render engine timestamp - 0x2358 + 64bit - gen7+

 * - Note this register returns an invalid value if using the default

 *   single instruction 8byte read, in order to workaround that use

 *   offset (0x2538 | 1) instead.

 *

 */



struct drm_i915_reset_stats {

	__u32 ctx_id;