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Commit 4d36f59d authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Add accessor macros for 64-bit performance counter registers. 



Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2789/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a1431b61

arch/mips/include/asm/mipsregs.h

+8 −0
Original line number Diff line number Diff line
@@ -1006,18 +1006,26 @@ do { \ 
#define write_c0_perfctrl0(val)	__write_32bit_c0_register($25, 0, val)

#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)

#define write_c0_perfcntr0(val)	__write_32bit_c0_register($25, 1, val)

#define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)

#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)

#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)

#define write_c0_perfctrl1(val)	__write_32bit_c0_register($25, 2, val)

#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)

#define write_c0_perfcntr1(val)	__write_32bit_c0_register($25, 3, val)

#define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)

#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)

#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)

#define write_c0_perfctrl2(val)	__write_32bit_c0_register($25, 4, val)

#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)

#define write_c0_perfcntr2(val)	__write_32bit_c0_register($25, 5, val)

#define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)

#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)

#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)

#define write_c0_perfctrl3(val)	__write_32bit_c0_register($25, 6, val)

#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)

#define write_c0_perfcntr3(val)	__write_32bit_c0_register($25, 7, val)

#define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)

#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)



/* RM9000 PerfCount performance counter register */

#define read_c0_perfcount()	__read_64bit_c0_register($25, 0)