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Commit 4d31c610 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Bjorn Helgaas
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PCI: imx6: Implement reset sequence for i.MX6+ 

I.MX6+ has a dedicated bit for resetting PCIe core, which should be used
instead of a regular reset sequence since using the latter will hang the
SoC.

This commit is based on c34068d48273e24d392d9a49a38be807954420ed from
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git



Tested-by: default avatarGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
parent e6f1fef0

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP 
and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"

- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"

- reg: base address and length of the PCIe controller

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

drivers/pci/host/pci-imx6.c

+21 −2
Original line number Diff line number Diff line
@@ -34,7 +34,8 @@ 


enum imx6_pcie_variants {

	IMX6Q,

	IMX6SX

	IMX6SX,

	IMX6QP,

};



struct imx6_pcie {
@@ -256,6 +257,11 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp) 
				   IMX6SX_GPR5_PCIE_BTNRST_RESET,

				   IMX6SX_GPR5_PCIE_BTNRST_RESET);

		break;

	case IMX6QP:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_SW_RST,

				   IMX6Q_GPR1_PCIE_SW_RST);

		break;

	case IMX6Q:

		/*

		 * If the bootloader already enabled the link we need some
@@ -310,6 +316,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 
		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);

		break;

	case IMX6QP: 		/* FALLTHROUGH */

	case IMX6Q:

		/* power up core phy and enable ref clock */

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
@@ -370,9 +377,20 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) 
					!imx6_pcie->gpio_active_high);

	}



	if (imx6_pcie->variant == IMX6SX)

	switch (imx6_pcie->variant) {

	case IMX6SX:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,

				   IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);

		break;

	case IMX6QP:

		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

				   IMX6Q_GPR1_PCIE_SW_RST, 0);



		usleep_range(200, 500);

		break;

	case IMX6Q:		/* Nothing to do */

		break;

	}



	return 0;
@@ -718,6 +736,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) 
static const struct of_device_id imx6_pcie_of_match[] = {

	{ .compatible = "fsl,imx6q-pcie",  .data = (void *)IMX6Q,  },

	{ .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },

	{ .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },

	{},

};

MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

+1 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ 
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX	BIT(0)



#define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)

#define IMX6Q_GPR1_PCIE_SW_RST			BIT(29)

#define IMX6Q_GPR1_PCIE_EXIT_L1			BIT(28)

#define IMX6Q_GPR1_PCIE_RDY_L23			BIT(27)

#define IMX6Q_GPR1_PCIE_ENTER_L1		BIT(26)