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Commit 4ca0d819 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf list: Fix documentation of :ppp 



Correctly document what is implemented for :ppp on Intel CPUs in recent
kernels.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Acked-by: default avatarJiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1458575793-12091-2-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 3c52b658

tools/perf/Documentation/perf-list.txt

+4 −2
Original line number Original line Diff line number Diff line
@@ -40,10 +40,12 @@ address should be. The 'p' modifier can be specified multiple times: 
 0 - SAMPLE_IP can have arbitrary skid

 0 - SAMPLE_IP can have arbitrary skid

 1 - SAMPLE_IP must have constant skid

 1 - SAMPLE_IP must have constant skid

 2 - SAMPLE_IP requested to have 0 skid

 2 - SAMPLE_IP requested to have 0 skid

 3 - SAMPLE_IP must have 0 skid

 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid

     sample shadowing effects.





For Intel systems precise event sampling is implemented with PEBS

For Intel systems precise event sampling is implemented with PEBS

which supports up to precise-level 2.

which supports up to precise-level 2, and precise level 3 for

some special cases





On AMD systems it is implemented using IBS (up to precise-level 2).

On AMD systems it is implemented using IBS (up to precise-level 2).

The precise modifier works with event types 0x76 (cpu-cycles, CPU

The precise modifier works with event types 0x76 (cpu-cycles, CPU