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Commit 4c6c03be authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask 



While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5575f03a

drivers/gpu/drm/i915/i915_irq.c

+10 −5
Original line number Diff line number Diff line
@@ -3169,14 +3169,19 @@ static void gen8_irq_reset(struct drm_device *dev) 
	ibx_irq_reset(dev);

}



void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)

void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,

				     unsigned int pipe_mask)

{

	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;



	spin_lock_irq(&dev_priv->irq_lock);

	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],

	if (pipe_mask & 1 << PIPE_B)

		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,

				  dev_priv->de_irq_mask[PIPE_B],

				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);

	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],

	if (pipe_mask & 1 << PIPE_C)

		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,

				  dev_priv->de_irq_mask[PIPE_C],

				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);

	spin_unlock_irq(&dev_priv->irq_lock);

}

drivers/gpu/drm/i915/intel_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -840,7 +840,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) 
}



int intel_get_crtc_scanline(struct intel_crtc *crtc);

void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);

void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,

				     unsigned int pipe_mask);



/* intel_crt.c */

void intel_crt_init(struct drm_device *dev);

drivers/gpu/drm/i915/intel_runtime_pm.c

+2 −1
Original line number Diff line number Diff line
@@ -195,7 +195,8 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);



	if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))

		gen8_irq_power_well_post_enable(dev_priv);

		gen8_irq_power_well_post_enable(dev_priv,

						1 << PIPE_C | 1 << PIPE_B);

}



static void hsw_set_power_well(struct drm_i915_private *dev_priv,