Merge "ARM: dts: msm: Add qusb-phy-host-init-seq on SDM670" (4c5541c7) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/usb/msm-phy.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -186,6 +186,7 @@ Optional properties:
		state when attached in host mode and "suspend" state when detached.
		- qcom,tune2-efuse-correction: The value to be adjusted from fused value for
		improved rise/fall times.
		- qcom,host-chirp-erratum: Indicates host chirp fix is required.
		- nvmem-cells: specifies the handle to represent the SoC revision.
		usually it is defined by qfprom device node.
		- nvmem-cell-names: specifies the given nvmem cell name as defined in

arch/arm64/boot/dts/qcom/sdm670-usb.dtsi

+21 −0

Original line number	Diff line number	Diff line
		@@ -35,6 +35,27 @@
		vdd-supply = <&pm660l_l1>;
		vdda18-supply = <&pm660_l10>;
		vdda33-supply = <&pm660l_l7>;
		qcom,host-chirp-erratum;
		qcom,qusb-phy-host-init-seq =
		/* <value reg_offset> */
		<0x23 0x210 /* PWR_CTRL1 */
		0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
		0x7c 0x18c /* PLL_CLOCK_INVERTERS */
		0x80 0x2c /* PLL_CMODE */
		0x0a 0x184 /* PLL_LOCK_DELAY */
		0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
		0x40 0x194 /* PLL_BIAS_CONTROL_1 */
		0x20 0x198 /* PLL_BIAS_CONTROL_2 */
		0x21 0x214 /* PWR_CTRL2 */
		0x08 0x220 /* IMP_CTRL1 */
		0x58 0x224 /* IMP_CTRL2 */
		0x45 0x240 /* TUNE1 */
		0x29 0x244 /* TUNE2 */
		0xca 0x248 /* TUNE3 */
		0x04 0x24c /* TUNE4 */
		0x03 0x250 /* TUNE5 */
		0x00 0x23c /* CHG_CTRL2 */
		0x22 0x210>; /* PWR_CTRL1 */
		qcom,qusb-phy-init-seq =
		/* <value reg_offset> */
		<0x23 0x210 /* PWR_CTRL1 */

drivers/usb/phy/phy-msm-qusb-v2.c

+17 −5

Original line number	Diff line number	Diff line
		@@ -71,6 +71,7 @@
		#define SQ_CTRL1_CHIRP_DISABLE 0x20
		#define SQ_CTRL2_CHIRP_DISABLE 0x80

		#define PORT_TUNE1_OVERRIDE_VAL 0xc5
		#define DEBUG_CTRL1_OVERRIDE_VAL 0x09

		/* PERIPH_SS_PHY_REFGEN_NORTH_BG_CTRL register bits */
		@@ -151,6 +152,7 @@ struct qusb_phy {

		struct hrtimer timer;
		int soc_min_rev;
		bool host_chirp_erratum;
		};

		#ifdef CONFIG_NVMEM
		@@ -198,6 +200,9 @@ static long qfprom_read(struct device dev, const char name)
		/* Reads the SoC version */
		static int qusb_phy_get_socrev(struct device dev, struct qusb_phy qphy)
		{
		if (!qphy->host_chirp_erratum)
		return 0;

		qphy->soc_min_rev = qfprom_read(dev, "minor_rev");
		if (qphy->soc_min_rev < 0)
		dev_err(dev, "failed getting soc_min_rev, err : %d\n",
		@@ -475,6 +480,15 @@ static void qusb_phy_host_init(struct usb_phy *phy)
		qusb_phy_write_seq(qphy->base, qphy->qusb_phy_host_init_seq,
		qphy->host_init_seq_len, 0);

		/* If soc revision is mentioned and host_chirp_erratum flag is set
		* then override TUNE1 and DEBUG_CTRL1
		*/
		if (qphy->soc_min_rev && qphy->host_chirp_erratum) {
		writel_relaxed(PORT_TUNE1_OVERRIDE_VAL,
		qphy->base + qphy->phy_reg[PORT_TUNE1]);
		writel_relaxed(DEBUG_CTRL1_OVERRIDE_VAL,
		qphy->base + qphy->phy_reg[DEBUG_CTRL1]);
		}
		/* Ensure above write is completed before turning ON ref clk */
		wmb();

		@@ -560,11 +574,6 @@ static int qusb_phy_init(struct usb_phy *phy)
		writel_relaxed(BIAS_CTRL_2_OVERRIDE_VAL,
		qphy->base + qphy->phy_reg[BIAS_CTRL_2]);

		/* if soc revision is mentioned override DEBUG_CTRL1 value */
		if (qphy->soc_min_rev)
		writel_relaxed(DEBUG_CTRL1_OVERRIDE_VAL,
		qphy->base + qphy->phy_reg[DEBUG_CTRL1]);

		/* ensure above writes are completed before re-enabling PHY */
		wmb();

		@@ -1170,6 +1179,9 @@ static int qusb_phy_probe(struct platform_device *pdev)
		return -ENOMEM;
		}

		qphy->host_chirp_erratum = of_property_read_bool(dev->of_node,
		"qcom,host-chirp-erratum");

		ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level",
		(u32 *) qphy->vdd_levels,
		ARRAY_SIZE(qphy->vdd_levels));