Loading arch/arm64/include/asm/assembler.h +2 −2 Original line number Diff line number Diff line Loading @@ -453,9 +453,9 @@ alternative_endif .endm /* * Errata workaround post TTBR0_EL1 update. * Errata workaround post TTBRx_EL1 update. */ .macro post_ttbr0_update_workaround .macro post_ttbr_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu Loading arch/arm64/include/asm/kernel-pgtable.h +10 −2 Original line number Diff line number Diff line Loading @@ -78,8 +78,16 @@ /* * Initial memory map attributes. */ #define SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) #define SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #define _SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) #define _SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 #define SWAPPER_PTE_FLAGS (_SWAPPER_PTE_FLAGS | PTE_NG) #define SWAPPER_PMD_FLAGS (_SWAPPER_PMD_FLAGS | PMD_SECT_NG) #else #define SWAPPER_PTE_FLAGS _SWAPPER_PTE_FLAGS #define SWAPPER_PMD_FLAGS _SWAPPER_PMD_FLAGS #endif #if ARM64_SWAPPER_USES_SECTION_MAPS #define SWAPPER_MM_MMUFLAGS (PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS) Loading arch/arm64/include/asm/mmu.h +3 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,9 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H #define USER_ASID_FLAG (UL(1) << 48) typedef struct { atomic64_t id; void *vdso; Loading arch/arm64/include/asm/mmu_context.h +7 −0 Original line number Diff line number Diff line Loading @@ -57,6 +57,13 @@ static inline void cpu_set_reserved_ttbr0(void) isb(); } static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) { BUG_ON(pgd == swapper_pg_dir); cpu_set_reserved_ttbr0(); cpu_do_switch_mm(virt_to_phys(pgd),mm); } /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in Loading arch/arm64/include/asm/pgtable-hwdef.h +1 −0 Original line number Diff line number Diff line Loading @@ -272,6 +272,7 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) #define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) Loading Loading
arch/arm64/include/asm/assembler.h +2 −2 Original line number Diff line number Diff line Loading @@ -453,9 +453,9 @@ alternative_endif .endm /* * Errata workaround post TTBR0_EL1 update. * Errata workaround post TTBRx_EL1 update. */ .macro post_ttbr0_update_workaround .macro post_ttbr_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu Loading
arch/arm64/include/asm/kernel-pgtable.h +10 −2 Original line number Diff line number Diff line Loading @@ -78,8 +78,16 @@ /* * Initial memory map attributes. */ #define SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) #define SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #define _SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) #define _SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 #define SWAPPER_PTE_FLAGS (_SWAPPER_PTE_FLAGS | PTE_NG) #define SWAPPER_PMD_FLAGS (_SWAPPER_PMD_FLAGS | PMD_SECT_NG) #else #define SWAPPER_PTE_FLAGS _SWAPPER_PTE_FLAGS #define SWAPPER_PMD_FLAGS _SWAPPER_PMD_FLAGS #endif #if ARM64_SWAPPER_USES_SECTION_MAPS #define SWAPPER_MM_MMUFLAGS (PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS) Loading
arch/arm64/include/asm/mmu.h +3 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,9 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H #define USER_ASID_FLAG (UL(1) << 48) typedef struct { atomic64_t id; void *vdso; Loading
arch/arm64/include/asm/mmu_context.h +7 −0 Original line number Diff line number Diff line Loading @@ -57,6 +57,13 @@ static inline void cpu_set_reserved_ttbr0(void) isb(); } static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) { BUG_ON(pgd == swapper_pg_dir); cpu_set_reserved_ttbr0(); cpu_do_switch_mm(virt_to_phys(pgd),mm); } /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in Loading
arch/arm64/include/asm/pgtable-hwdef.h +1 −0 Original line number Diff line number Diff line Loading @@ -272,6 +272,7 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) #define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) Loading