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Commit 4a9a40df authored by Laxminath Kasam's avatar Laxminath Kasam Committed by Banajit Goswami
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ASoC: sdm660_cdc: Avoid unclocked register access to digital codec 



In particular SSR scenario, digital codec access happens without
clock enabled. While SSR down event notification in progress,
APR driver blocks request to DSP to enable clock since APR already
received down event. regmap access to digital codec register results in
AHB timeout error. If DSP clock enable request fails, set the regmap
access cache only mode to avoid any register access.

CRs-Fixed: 2034468
Change-Id: Id1141339d2673920167ed7ac74b13b6fee05173f
Signed-off-by: default avatarLaxminath Kasam <lkasam@codeaurora.org>
parent 6f71b80b

sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c

+9 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include "msm-digital-cdc.h"

#include "msm-cdc-common.h"

#include "../../msm/sdm660-common.h"

#include "../../../../drivers/base/regmap/internal.h"



#define DRV_NAME "msm_digital_codec"

#define MCLK_RATE_9P6MHZ        9600000
@@ -71,6 +72,8 @@ static int msm_digcdc_clock_control(bool flag) 
{

	int ret = -EINVAL;

	struct msm_asoc_mach_data *pdata = NULL;

	struct msm_dig_priv *msm_dig_cdc =

				snd_soc_codec_get_drvdata(registered_digcodec);



	pdata = snd_soc_card_get_drvdata(registered_digcodec->component.card);
@@ -84,6 +87,12 @@ static int msm_digcdc_clock_control(bool flag) 
			if (ret < 0) {

				pr_err("%s:failed to enable the MCLK\n",

				       __func__);

				/*

				 * Avoid access to lpass register

				 * as clock enable failed during SSR.

				 */

				if (ret == -ENODEV)

					msm_dig_cdc->regmap->cache_only = true;

				mutex_unlock(&pdata->cdc_int_mclk0_mutex);

				return ret;

			}