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Commit 4a89c308 authored by Ley Foon Tan's avatar Ley Foon Tan
Browse files

nios2: fix cache coherency issue when debug with gdb 



Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.

Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.


Signed-off-by: default avatarLey Foon Tan <lftan@altera.com>
parent e3e29f99

arch/nios2/kernel/entry.S

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ ENTRY(inthandler) 
 ***********************************************************************

 */

ENTRY(handle_trap)

	ldw	r24, -4(ea)	/* instruction that caused the exception */

	ldwio	r24, -4(ea)	/* instruction that caused the exception */

	srli	r24, r24, 4

	andi	r24, r24, 0x7c

	movia	r9,trap_table

arch/nios2/mm/cacheflush.c

+0 −3
Original line number Diff line number Diff line
@@ -23,9 +23,6 @@ static void __flush_dcache(unsigned long start, unsigned long end) 
	end += (cpuinfo.dcache_line_size - 1);

	end &= ~(cpuinfo.dcache_line_size - 1);



	if (end > start + cpuinfo.dcache_size)

		end = start + cpuinfo.dcache_size;



	for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {

		__asm__ __volatile__ ("   flushda 0(%0)\n"

					: /* Outputs */