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Commit 4a58908f authored by Borislav Petkov's avatar Borislav Petkov Committed by Greg Kroah-Hartman
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x86/speculation: Use synthetic bits for IBRS/IBPB/STIBP 



commit e7c587da125291db39ddf1f49b18e5970adbac17 upstream

Intel and AMD have different CPUID bits hence for those use synthetic bits
which get set on the respective vendor's in init_speculation_control(). So
that debacles like what the commit message of

  c65732e4f721 ("x86/cpu: Restore CPUID_8000_0008_EBX reload")

talks about don't happen anymore.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Tested-by: default avatarJörg Otte <jrg.otte@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Link: https://lkml.kernel.org/r/20180504161815.GG9257@pd.tnic


Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 69e9b0b1

arch/x86/include/asm/cpufeatures.h

+8 −4
Original line number Diff line number Diff line
@@ -206,6 +206,9 @@ 
#define X86_FEATURE_USE_IBRS_FW	( 7*32+22) /* "" Use IBRS during runtime firmware calls */

#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */

#define X86_FEATURE_AMD_SSBD	( 7*32+24) /* "" AMD SSBD implementation */

#define X86_FEATURE_IBRS	( 7*32+25) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB	( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP	( 7*32+27) /* Single Thread Indirect Branch Predictors */



/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
@@ -263,9 +266,9 @@ 
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */

#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF	(13*32+1) /* Instructions Retired Count */

#define X86_FEATURE_IBPB	(13*32+12) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_IBRS	(13*32+14) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_STIBP	(13*32+15) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_AMD_IBPB	(13*32+12) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBRS	(13*32+14) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_AMD_STIBP	(13*32+15) /* Single Thread Indirect Branch Predictors */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */

#define X86_FEATURE_DTHERM	(14*32+ 0) /* Digital Thermal Sensor */
@@ -301,6 +304,7 @@ 
#define X86_FEATURE_SUCCOR	(17*32+1) /* Uncorrectable error containment and recovery */

#define X86_FEATURE_SMCA	(17*32+3) /* Scalable MCA */





/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

arch/x86/kernel/cpu/common.c

+10 −4
Original line number Diff line number Diff line
@@ -725,17 +725,23 @@ static void init_speculation_control(struct cpuinfo_x86 *c) 
	 * and they also have a different bit for STIBP support. Also,

	 * a hypervisor might have set the individual AMD bits even on

	 * Intel CPUs, for finer-grained selection of what's available.

	 *

	 * We use the AMD bits in 0x8000_0008 EBX as the generic hardware

	 * features, which are visible in /proc/cpuinfo and used by the

	 * kernel. So set those accordingly from the Intel bits.

	 */

	if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {

		set_cpu_cap(c, X86_FEATURE_IBRS);

		set_cpu_cap(c, X86_FEATURE_IBPB);

	}



	if (cpu_has(c, X86_FEATURE_INTEL_STIBP))

		set_cpu_cap(c, X86_FEATURE_STIBP);



	if (cpu_has(c, X86_FEATURE_AMD_IBRS))

		set_cpu_cap(c, X86_FEATURE_IBRS);



	if (cpu_has(c, X86_FEATURE_AMD_IBPB))

		set_cpu_cap(c, X86_FEATURE_IBPB);



	if (cpu_has(c, X86_FEATURE_AMD_STIBP))

		set_cpu_cap(c, X86_FEATURE_STIBP);

}



void get_cpu_cap(struct cpuinfo_x86 *c)

arch/x86/kvm/cpuid.c

+5 −5
Original line number Diff line number Diff line
@@ -357,7 +357,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 


	/* cpuid 0x80000008.ebx */

	const u32 kvm_cpuid_8000_0008_ebx_x86_features =

		F(IBPB) | F(IBRS);

		F(AMD_IBPB) | F(AMD_IBRS);



	/* cpuid 0xC0000001.edx */

	const u32 kvm_cpuid_C000_0001_edx_x86_features =
@@ -619,10 +619,10 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 
		entry->eax = g_phys_as | (virt_as << 8);

		entry->edx = 0;

		/* IBRS and IBPB aren't necessarily present in hardware cpuid */

		if (boot_cpu_has(X86_FEATURE_IBPB))

			entry->ebx |= F(IBPB);

		if (boot_cpu_has(X86_FEATURE_IBRS))

			entry->ebx |= F(IBRS);

		if (boot_cpu_has(X86_FEATURE_AMD_IBPB))

			entry->ebx |= F(AMD_IBPB);

		if (boot_cpu_has(X86_FEATURE_AMD_IBRS))

			entry->ebx |= F(AMD_IBRS);

		entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;

		cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);

		break;

arch/x86/kvm/cpuid.h

+2 −2
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ static inline bool guest_cpuid_has_ibpb(struct kvm_vcpu *vcpu) 
	struct kvm_cpuid_entry2 *best;



	best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);

	if (best && (best->ebx & bit(X86_FEATURE_IBPB)))

	if (best && (best->ebx & bit(X86_FEATURE_AMD_IBPB)))

		return true;

	best = kvm_find_cpuid_entry(vcpu, 7, 0);

	return best && (best->edx & bit(X86_FEATURE_SPEC_CTRL));
@@ -176,7 +176,7 @@ static inline bool guest_cpuid_has_spec_ctrl(struct kvm_vcpu *vcpu) 
	struct kvm_cpuid_entry2 *best;



	best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);

	if (best && (best->ebx & bit(X86_FEATURE_IBRS)))

	if (best && (best->ebx & bit(X86_FEATURE_AMD_IBRS)))

		return true;

	best = kvm_find_cpuid_entry(vcpu, 7, 0);

	return best && (best->edx & (bit(X86_FEATURE_SPEC_CTRL) | bit(X86_FEATURE_SSBD)));