Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +13 −0 Original line number Diff line number Diff line Loading @@ -1685,6 +1685,19 @@ int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl) return rc; } int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl) { if (!dsi_ctrl) return -EINVAL; mutex_lock(&dsi_ctrl->ctrl_lock); dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw); mutex_unlock(&dsi_ctrl->ctrl_lock); pr_debug("[DSI_%d]Soft reset complete\n", dsi_ctrl->index); return 0; } /** * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware. * @dsi_ctrl: DSI controller handle. Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +15 −0 Original line number Diff line number Diff line Loading @@ -328,6 +328,21 @@ int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl); */ int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable); /** * dsi_ctrl_soft_reset() - perform a soft reset on DSI controller * @dsi_ctrl: DSI controller handle. * * The video, command and controller engines will be disabled before the * reset is triggered. After, the engines will be re-enabled to the same state * as before the reset. * * If the reset is done while MDP timing engine is turned on, the video * engine should be re-enabled only during the vertical blanking time. * * Return: error code */ int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl); /** * dsi_ctrl_host_init() - Initialize DSI host hardware. * @dsi_ctrl: DSI controller handle. Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h +4 −4 Original line number Diff line number Diff line Loading @@ -346,12 +346,12 @@ struct dsi_ctrl_hw_ops { * soft_reset() - perform a soft reset on DSI controller * @ctrl: Pointer to the controller host hardware. * * The video, command and controller engines will be disable before the * reset is triggered. These engines will not be enabled after the reset * is complete. Caller must re-enable the engines. * The video, command and controller engines will be disabled before the * reset is triggered. After, the engines will be re-enabled to the same * state as before the reset. * * If the reset is done while MDP timing engine is turned on, the video * enigne should be re-enabled only during the vertical blanking time. * engine should be re-enabled only during the vertical blanking time. */ void (*soft_reset)(struct dsi_ctrl_hw *ctrl); Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +24 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,30 @@ int dsi_display_set_backlight(void *display, u32 bl_lvl) return rc; } int dsi_display_soft_reset(void *display) { struct dsi_display *dsi_display; struct dsi_display_ctrl *ctrl; int rc = 0; int i; if (!display) return -EINVAL; dsi_display = display; for (i = 0 ; i < dsi_display->ctrl_count; i++) { ctrl = &dsi_display->ctrl[i]; rc = dsi_ctrl_soft_reset(ctrl->ctrl); if (rc) { pr_err("[%s] failed to soft reset host_%d, rc=%d\n", dsi_display->name, i, rc); break; } } return rc; } static ssize_t debugfs_dump_info_read(struct file *file, char __user *buff, size_t count, Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.h +15 −0 Original line number Diff line number Diff line Loading @@ -391,4 +391,19 @@ int dsi_display_clock_gate(struct dsi_display *display, bool enable); int dsi_dispaly_static_frame(struct dsi_display *display, bool enable); int dsi_display_set_backlight(void *display, u32 bl_lvl); /** * dsi_display_soft_reset() - perform a soft reset on DSI controller * @display: Handle to display * * The video, command and controller engines will be disabled before the * reset is triggered. After, the engines will be re-enabled to the same state * as before the reset. * * If the reset is done while MDP timing engine is turned on, the video * engine should be re-enabled only during the vertical blanking time. * * Return: error code */ int dsi_display_soft_reset(void *display); #endif /* _DSI_DISPLAY_H_ */ Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +13 −0 Original line number Diff line number Diff line Loading @@ -1685,6 +1685,19 @@ int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl) return rc; } int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl) { if (!dsi_ctrl) return -EINVAL; mutex_lock(&dsi_ctrl->ctrl_lock); dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw); mutex_unlock(&dsi_ctrl->ctrl_lock); pr_debug("[DSI_%d]Soft reset complete\n", dsi_ctrl->index); return 0; } /** * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware. * @dsi_ctrl: DSI controller handle. Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +15 −0 Original line number Diff line number Diff line Loading @@ -328,6 +328,21 @@ int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl); */ int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable); /** * dsi_ctrl_soft_reset() - perform a soft reset on DSI controller * @dsi_ctrl: DSI controller handle. * * The video, command and controller engines will be disabled before the * reset is triggered. After, the engines will be re-enabled to the same state * as before the reset. * * If the reset is done while MDP timing engine is turned on, the video * engine should be re-enabled only during the vertical blanking time. * * Return: error code */ int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl); /** * dsi_ctrl_host_init() - Initialize DSI host hardware. * @dsi_ctrl: DSI controller handle. Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h +4 −4 Original line number Diff line number Diff line Loading @@ -346,12 +346,12 @@ struct dsi_ctrl_hw_ops { * soft_reset() - perform a soft reset on DSI controller * @ctrl: Pointer to the controller host hardware. * * The video, command and controller engines will be disable before the * reset is triggered. These engines will not be enabled after the reset * is complete. Caller must re-enable the engines. * The video, command and controller engines will be disabled before the * reset is triggered. After, the engines will be re-enabled to the same * state as before the reset. * * If the reset is done while MDP timing engine is turned on, the video * enigne should be re-enabled only during the vertical blanking time. * engine should be re-enabled only during the vertical blanking time. */ void (*soft_reset)(struct dsi_ctrl_hw *ctrl); Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +24 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,30 @@ int dsi_display_set_backlight(void *display, u32 bl_lvl) return rc; } int dsi_display_soft_reset(void *display) { struct dsi_display *dsi_display; struct dsi_display_ctrl *ctrl; int rc = 0; int i; if (!display) return -EINVAL; dsi_display = display; for (i = 0 ; i < dsi_display->ctrl_count; i++) { ctrl = &dsi_display->ctrl[i]; rc = dsi_ctrl_soft_reset(ctrl->ctrl); if (rc) { pr_err("[%s] failed to soft reset host_%d, rc=%d\n", dsi_display->name, i, rc); break; } } return rc; } static ssize_t debugfs_dump_info_read(struct file *file, char __user *buff, size_t count, Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.h +15 −0 Original line number Diff line number Diff line Loading @@ -391,4 +391,19 @@ int dsi_display_clock_gate(struct dsi_display *display, bool enable); int dsi_dispaly_static_frame(struct dsi_display *display, bool enable); int dsi_display_set_backlight(void *display, u32 bl_lvl); /** * dsi_display_soft_reset() - perform a soft reset on DSI controller * @display: Handle to display * * The video, command and controller engines will be disabled before the * reset is triggered. After, the engines will be re-enabled to the same state * as before the reset. * * If the reset is done while MDP timing engine is turned on, the video * engine should be re-enabled only during the vertical blanking time. * * Return: error code */ int dsi_display_soft_reset(void *display); #endif /* _DSI_DISPLAY_H_ */
