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Commit 4a17b8b4 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add DSI PHY refgen for sdm845 v2"

parents 8b046ea3 e38166ea

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

+3 −100
Original line number Diff line number Diff line
@@ -414,109 +414,12 @@ 
			compatible = "qcom,msm-ext-disp-audio-codec-rx";

		};

	};

};



	sde_dp: qcom,dp_display@0{

		cell-index = <0>;

		compatible = "qcom,dp-display";



		gdsc-supply = <&mdss_core_gdsc>;

		vdda-1p2-supply = <&pm8998_l26>;

		vdda-0p9-supply = <&pm8998_l1>;



		reg =	<0xae90000 0xa84>,

			<0x88eaa00 0x200>,

			<0x88ea200 0x200>,

			<0x88ea600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ea030 0x10>,

			<0x88e8000 0x20>,

			<0x0aee1000 0x034>;

		reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <12 0>;



		clocks =  <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;

		clock-names = "core_aux_clk", "core_usb_ref_clk_src",

			"core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk",

			"ctrl_link_iface_clk", "ctrl_pixel_clk",

			"crypto_clk", "pixel_clk_rcg", "pixel_parent";



&sde_dp {

	qcom,dp-usbpd-detection = <&pmi8998_pdphy>;

	qcom,ext-disp = <&ext_disp>;



		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13 23 1d];

		qcom,aux-cfg2-settings = [28 24];

		qcom,aux-cfg3-settings = [2c 00];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 26];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 bb];

		qcom,aux-cfg9-settings = [44 03];



		qcom,max-pclk-frequency-khz = <675000>;



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <4>;

			};

		};



		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <32>;

			};

		};

	};

};



&sde_dp {

	pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";

	pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;

	pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+83 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <dt-bindings/clock/mdss-10nm-pll-clk.h>



&soc {

	mdss_mdp: qcom,mdss_mdp@ae00000 {
@@ -535,4 +536,86 @@ 
		};

	};



	sde_dp: qcom,dp_display@0{

		cell-index = <0>;

		compatible = "qcom,dp-display";



		gdsc-supply = <&mdss_core_gdsc>;

		vdda-1p2-supply = <&pm8998_l26>;

		vdda-0p9-supply = <&pm8998_l1>;



		reg =	<0xae90000 0xa84>,

			<0x88eaa00 0x200>,

			<0x88ea200 0x200>,

			<0x88ea600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ea030 0x10>,

			<0x88e8000 0x20>,

			<0x0aee1000 0x034>;

		reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",

			"dp_mmss_cc", "qfprom_physical", "dp_pll",

			"usb3_dp_com", "hdcp_physical";



		interrupt-parent = <&mdss_mdp>;

		interrupts = <12 0>;



		clocks =  <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,

			 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,

			 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;

		clock-names = "core_aux_clk", "core_usb_ref_clk_src",

			"core_usb_ref_clk", "core_usb_cfg_ahb_clk",

			"core_usb_pipe_clk", "ctrl_link_clk",

			"ctrl_link_iface_clk", "ctrl_pixel_clk",

			"crypto_clk", "pixel_clk_rcg", "pixel_parent";



		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 13 23 1d];

		qcom,aux-cfg2-settings = [28 24];

		qcom,aux-cfg3-settings = [2c 00];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 26];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 bb];

		qcom,aux-cfg9-settings = [44 03];



		qcom,max-pclk-frequency-khz = <675000>;



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <4>;

			};

		};



		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <36000>;

				qcom,supply-disable-load = <32>;

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdm845-v2.dtsi

+48 −0
Original line number Diff line number Diff line
@@ -1207,6 +1207,54 @@ 
	qcom,sde-min-core-ib-kbps = <4800000>;

};



&mdss_dsi0 {

	qcom,core-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,core-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "refgen";

			qcom,supply-min-voltage = <0>;

			qcom,supply-max-voltage = <0>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

};



&mdss_dsi1 {

	qcom,core-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,core-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "refgen";

			qcom,supply-min-voltage = <0>;

			qcom,supply-max-voltage = <0>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

};



&sde_dp {

	qcom,core-supply-entries {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,core-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "refgen";

			qcom,supply-min-voltage = <0>;

			qcom,supply-max-voltage = <0>;

			qcom,supply-enable-load = <0>;

			qcom,supply-disable-load = <0>;

		};

	};

};



&energy_costs {

	CPU_COST_0: core-cost0 {

		busy-cost-data = <