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Commit 498cd5c3 authored by Marc Zyngier's avatar Marc Zyngier Committed by Christoffer Dall
Browse files

arm64: KVM: Add workaround for Cortex-A57 erratum 834220 



Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults
when a Stage 1 permission fault or device alignment fault should
have been reported.

This patch implements the workaround (which is to validate that the
Stage-1 translation actually succeeds) by using code patching.

Cc: stable@vger.kernel.org
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent c0f09634

arch/arm64/Kconfig

+21 −0
Original line number Diff line number Diff line
@@ -316,6 +316,27 @@ config ARM64_ERRATUM_832075 


	  If unsure, say Y.



config ARM64_ERRATUM_834220

	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"

	depends on KVM

	default y

	help

	  This option adds an alternative code sequence to work around ARM

	  erratum 834220 on Cortex-A57 parts up to r1p2.



	  Affected Cortex-A57 parts might report a Stage 2 translation

	  fault as the result of a Stage 1 fault for load crossing a

	  page boundary when there is a permission or device memory

	  alignment fault at Stage 1 and a translation fault at Stage 2.



	  The workaround is to verify that the Stage 1 translation

	  doesn't generate a fault before handling the Stage 2 fault.

	  Please note that this does not necessarily enable the workaround,

	  as it depends on the alternative framework, which will only patch

	  the kernel if an affected CPU is detected.



	  If unsure, say Y.



config ARM64_ERRATUM_845719

	bool "Cortex-A53: 845719: a load might read incorrect data"

	depends on COMPAT

arch/arm64/include/asm/cpufeature.h

+2 −1
Original line number Diff line number Diff line
@@ -29,8 +29,9 @@ 
#define ARM64_HAS_PAN				4

#define ARM64_HAS_LSE_ATOMICS			5

#define ARM64_WORKAROUND_CAVIUM_23154		6

#define ARM64_WORKAROUND_834220			7



#define ARM64_NCAPS				7

#define ARM64_NCAPS				8



#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+9 −0
Original line number Diff line number Diff line
@@ -75,6 +75,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
			   (1 << MIDR_VARIANT_SHIFT) | 2),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_834220

	{

	/* Cortex-A57 r0p0 - r1p2 */

		.desc = "ARM erratum 834220",

		.capability = ARM64_WORKAROUND_834220,

		MIDR_RANGE(MIDR_CORTEX_A57, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 2),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_845719

	{

	/* Cortex-A53 r0p[01234] */

arch/arm64/kvm/hyp.S

+6 −0
Original line number Diff line number Diff line
@@ -1015,9 +1015,15 @@ el1_trap: 
	b.ne	1f		// Not an abort we care about



	/* This is an abort. Check for permission fault */

alternative_if_not ARM64_WORKAROUND_834220

	and	x2, x1, #ESR_ELx_FSC_TYPE

	cmp	x2, #FSC_PERM

	b.ne	1f		// Not a permission fault

alternative_else

	nop			// Use the permission fault path to

	nop			// check for a valid S1 translation,

	nop			// regardless of the ESR value.

alternative_endif



	/*

	 * Check for Stage-1 page table walk, which is guaranteed