Loading arch/arm64/boot/dts/qcom/sdm845.dtsi +18 −5 Original line number Diff line number Diff line Loading @@ -707,7 +707,7 @@ }; clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sdm845"; compatible = "qcom,gcc-sdm845", "syscon"; reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -717,7 +717,7 @@ }; clock_videocc: qcom,videocc@ab00000 { compatible = "qcom,video_cc-sdm845"; compatible = "qcom,video_cc-sdm845", "syscon"; reg = <0xab00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -726,7 +726,7 @@ }; clock_camcc: qcom,camcc@ad00000 { compatible = "qcom,cam_cc-sdm845"; compatible = "qcom,cam_cc-sdm845", "syscon"; reg = <0xad00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -736,7 +736,7 @@ }; clock_dispcc: qcom,dispcc@af00000 { compatible = "qcom,dispcc-sdm845"; compatible = "qcom,dispcc-sdm845", "syscon"; reg = <0xaf00000 0x100000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -745,7 +745,7 @@ }; clock_gpucc: qcom,gpucc@5090000 { compatible = "qcom,gpucc-sdm845"; compatible = "qcom,gpucc-sdm845", "syscon"; reg = <0x5090000 0x9000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading Loading @@ -887,6 +887,19 @@ mbox-names = "apps"; }; clock_debug: qcom,cc-debug@100000 { compatible = "qcom,debugcc-sdm845"; qcom,cc-count = <5>; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,camcc = <&clock_camcc>; qcom,dispcc = <&clock_dispcc>; qcom,gpucc = <&clock_gpucc>; clock-names = "xo_clk_src"; clocks = <&clock_rpmh RPMH_CXO_CLK>; #clock-cells = <1>; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xda8>; /* PHY regs */ reg-names = "phy_mem"; Loading Loading
arch/arm64/boot/dts/qcom/sdm845.dtsi +18 −5 Original line number Diff line number Diff line Loading @@ -707,7 +707,7 @@ }; clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sdm845"; compatible = "qcom,gcc-sdm845", "syscon"; reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -717,7 +717,7 @@ }; clock_videocc: qcom,videocc@ab00000 { compatible = "qcom,video_cc-sdm845"; compatible = "qcom,video_cc-sdm845", "syscon"; reg = <0xab00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -726,7 +726,7 @@ }; clock_camcc: qcom,camcc@ad00000 { compatible = "qcom,cam_cc-sdm845"; compatible = "qcom,cam_cc-sdm845", "syscon"; reg = <0xad00000 0x10000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -736,7 +736,7 @@ }; clock_dispcc: qcom,dispcc@af00000 { compatible = "qcom,dispcc-sdm845"; compatible = "qcom,dispcc-sdm845", "syscon"; reg = <0xaf00000 0x100000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading @@ -745,7 +745,7 @@ }; clock_gpucc: qcom,gpucc@5090000 { compatible = "qcom,gpucc-sdm845"; compatible = "qcom,gpucc-sdm845", "syscon"; reg = <0x5090000 0x9000>; reg-names = "cc_base"; vdd_cx-supply = <&pm8998_s9_level>; Loading Loading @@ -887,6 +887,19 @@ mbox-names = "apps"; }; clock_debug: qcom,cc-debug@100000 { compatible = "qcom,debugcc-sdm845"; qcom,cc-count = <5>; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,camcc = <&clock_camcc>; qcom,dispcc = <&clock_dispcc>; qcom,gpucc = <&clock_gpucc>; clock-names = "xo_clk_src"; clocks = <&clock_rpmh RPMH_CXO_CLK>; #clock-cells = <1>; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xda8>; /* PHY regs */ reg-names = "phy_mem"; Loading