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Commit 48404c1e authored by Sonika Jindal's avatar Sonika Jindal Committed by Daniel Vetter
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drm/i915: Add 180 degree primary plane rotation support 



Primary planes support 180 degree rotation. Expose the feature
through rotation drm property.

v2: Calculating linear/tiled offsets based on pipe source width and
height. Added 180 degree rotation support in ironlake_update_plane.

v3: Checking if CRTC is active before issueing update_plane. Added
wait for vblank to make sure we dont overtake page flips. Disabling
FBC since it does not work with rotated planes.

v4: Updated rotation checks for pending flips, fbc disable. Creating
rotation property only for Gen4 onwards. Property resetting as part
of lastclose.

v5: Resetting property in i915_driver_lastclose properly for planes
and crtcs. Fixed linear offset calculation that was off by 1 w.r.t
width in i9xx_update_plane and ironlake_update_plane. Removed tab
based indentation and unnecessary braces in intel_crtc_set_property
and intel_update_fbc. FBC and flip related checks should be done only
for valid crtcs.

v6: Minor nits in FBC disable checks for comments in intel_crtc_set_property
and positioning the disable code in intel_update_fbc.

v7: In case rotation property on inactive crtc is updated, we return
successfully printing debug log as crtc is inactive and only property change
is preserved.

v8: update_plane is changed to update_primary_plane, crtc->fb is changed to
crtc->primary->fb  and return value of update_primary_plane is ignored.

v9: added rotation property to primary plane instead of crtc. Removing reset
of rotation property from lastclose. rotation_property is moved to
drm_mode_config, so drm layer will take care of resetting. Adding updation of
fbc when rotation is set to 0. Allowing rotation only if value is
different than old one.

v10: Calling intel_primary_plane_setplane instead of update_primary_plane in
set_property(Daniel).

v11: Using same set_property function for both primary and sprite, Adding
primary plane specific code in the same function (Matt).

v12: Removing disabling/ enabling of fbc from set_property because it is done
from intel_pipe_set_base. Other formatting

v13: we need to call disable_fbc before changing the rotation to 180,
disable_fbc from intel_pipe_set_base gets called very late, that will
be used to re-enable fbc if rotation is set to 0 (Ville).

Testcase: igt/kms_rotation_crc

Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarSagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarSonika Jindal <sonika.jindal@intel.com>
[danvet: Add FIXME to explain why we need the open-coded update_fbc
hunk to disable fbc when rotated 180 degree. And make checkpatch
happier.]
Acked-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ce54d85a

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4214,6 +4214,7 @@ enum punit_power_well { 
#define   DISPPLANE_NO_LINE_DOUBLE		0

#define   DISPPLANE_STEREO_POLARITY_FIRST	0

#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)

#define   DISPPLANE_ROTATE_180         (1<<15)

#define   DISPPLANE_TRICKLE_FEED_DISABLE	(1<<14) /* Ironlake */

#define   DISPPLANE_TILED			(1<<10)

#define _DSPAADDR				0x70184

drivers/gpu/drm/i915/intel_display.c

+71 −4
Original line number Diff line number Diff line
@@ -2378,6 +2378,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, 
	unsigned long linear_offset;

	u32 dspcntr;

	u32 reg = DSPCNTR(plane);

	int pixel_size;



	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);



	if (!intel_crtc->primary_enabled) {

		I915_WRITE(reg, 0);
@@ -2444,8 +2447,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, 
	if (IS_G4X(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	I915_WRITE(reg, dspcntr);



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);



	if (INTEL_INFO(dev)->gen >= 4) {
@@ -2458,6 +2459,21 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, 
		intel_crtc->dspaddr_offset = linear_offset;

	}



	if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {

		dspcntr |= DISPPLANE_ROTATE_180;



		x += (intel_crtc->config.pipe_src_w - 1);

		y += (intel_crtc->config.pipe_src_h - 1);



		/* Finding the last pixel of the last line of the display

		data and adding to linear_offset*/

		linear_offset +=

			(intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +

			(intel_crtc->config.pipe_src_w - 1) * pixel_size;

	}



	I915_WRITE(reg, dspcntr);



	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,

		      fb->pitches[0]);
@@ -2484,6 +2500,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, 
	unsigned long linear_offset;

	u32 dspcntr;

	u32 reg = DSPCNTR(plane);

	int pixel_size;



	pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);



	if (!intel_crtc->primary_enabled) {

		I915_WRITE(reg, 0);
@@ -2532,14 +2551,28 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, 
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	I915_WRITE(reg, dspcntr);



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	intel_crtc->dspaddr_offset =

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       fb->bits_per_pixel / 8,

					       fb->pitches[0]);

	linear_offset -= intel_crtc->dspaddr_offset;

	if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {

		dspcntr |= DISPPLANE_ROTATE_180;



		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {

			x += (intel_crtc->config.pipe_src_w - 1);

			y += (intel_crtc->config.pipe_src_h - 1);



			/* Finding the last pixel of the last line of the display

			data and adding to linear_offset*/

			linear_offset +=

				(intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +

				(intel_crtc->config.pipe_src_w - 1) * pixel_size;

		}

	}



	I915_WRITE(reg, dspcntr);



	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
@@ -11562,6 +11595,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, 
			     uint32_t src_w, uint32_t src_h)

{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
@@ -11674,6 +11708,24 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, 
		mutex_unlock(&dev->struct_mutex);



	} else {

		if (intel_crtc && intel_crtc->active &&

		    intel_crtc->primary_enabled) {

			/*

			 * FBC does not work on some platforms for rotated

			 * planes, so disable it when rotation is not 0 and

			 * update it when rotation is set back to 0.

			 *

			 * FIXME: This is redundant with the fbc update done in

			 * the primary plane enable function except that that

			 * one is done too late. We eventually need to unify

			 * this.

			 */

			if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&

			    dev_priv->fbc.plane == intel_crtc->plane &&

			    intel_plane->rotation != BIT(DRM_ROTATE_0)) {

				intel_disable_fbc(dev);

			}

		}

		ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);

		if (ret)

			return ret;
@@ -11707,6 +11759,7 @@ static const struct drm_plane_funcs intel_primary_plane_funcs = { 
	.update_plane = intel_primary_plane_setplane,

	.disable_plane = intel_primary_plane_disable,

	.destroy = intel_plane_destroy,

	.set_property = intel_plane_set_property

};



static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
@@ -11724,6 +11777,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, 
	primary->max_downscale = 1;

	primary->pipe = pipe;

	primary->plane = pipe;

	primary->rotation = BIT(DRM_ROTATE_0);

	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)

		primary->plane = !pipe;
@@ -11739,6 +11793,19 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, 
				 &intel_primary_plane_funcs,

				 intel_primary_formats, num_formats,

				 DRM_PLANE_TYPE_PRIMARY);



	if (INTEL_INFO(dev)->gen >= 4) {

		if (!dev->mode_config.rotation_property)

			dev->mode_config.rotation_property =

				drm_mode_create_rotation_property(dev,

							BIT(DRM_ROTATE_0) |

							BIT(DRM_ROTATE_180));

		if (dev->mode_config.rotation_property)

			drm_object_attach_property(&primary->base.base,

				dev->mode_config.rotation_property,

				primary->rotation);

	}



	return &primary->base;

}

drivers/gpu/drm/i915/intel_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -1093,6 +1093,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);

void intel_flush_primary_plane(struct drm_i915_private *dev_priv,

			       enum plane plane);

int intel_plane_set_property(struct drm_plane *plane,

			     struct drm_property *prop,

			     uint64_t val);

int intel_plane_restore(struct drm_plane *plane);

void intel_plane_disable(struct drm_plane *plane);

int intel_sprite_set_colorkey(struct drm_device *dev, void *data,

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -581,6 +581,12 @@ void intel_update_fbc(struct drm_device *dev) 
			DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");

		goto out_disable;

	}

	if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&

	    to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {

		if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))

			DRM_DEBUG_KMS("Rotation unsupported, disabling\n");

		goto out_disable;

	}



	/* If the kernel debugger is active, always disable compression */

	if (in_dbg_master())

drivers/gpu/drm/i915/intel_sprite.c

+4 −4
Original line number Diff line number Diff line
@@ -1218,7 +1218,7 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 
	return ret;

}



static int intel_plane_set_property(struct drm_plane *plane,

int intel_plane_set_property(struct drm_plane *plane,

			     struct drm_property *prop,

			     uint64_t val)

{
@@ -1249,7 +1249,7 @@ int intel_plane_restore(struct drm_plane *plane) 
	if (!plane->crtc || !plane->fb)

		return 0;



	return intel_update_plane(plane, plane->crtc, plane->fb,

	return plane->funcs->update_plane(plane, plane->crtc, plane->fb,

				  intel_plane->crtc_x, intel_plane->crtc_y,

				  intel_plane->crtc_w, intel_plane->crtc_h,

				  intel_plane->src_x, intel_plane->src_y,