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Commit 47ae63e0 authored by Chris Wilson's avatar Chris Wilson
Browse files

Merge branch 'drm-intel-fixes' into drm-intel-next 

Apply the trivial conflicting regression fixes, but keep GPU semaphores
enabled.

Conflicts:
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/i915/i915_gem_execbuffer.c
parents c59a333f 467cffba

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -873,7 +873,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		int max_freq;



		/* RPSTAT1 is in the GT power well */

		__gen6_force_wake_get(dev_priv);

		__gen6_gt_force_wake_get(dev_priv);



		rpstat = I915_READ(GEN6_RPSTAT1);

		rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
@@ -918,7 +918,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   max_freq * 100);



		__gen6_force_wake_put(dev_priv);

		__gen6_gt_force_wake_put(dev_priv);

	} else {

		seq_printf(m, "no P-state info available\n");

	}

drivers/gpu/drm/i915/i915_drv.c

+15 −2
Original line number Diff line number Diff line
@@ -49,6 +49,9 @@ module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); 
unsigned int i915_powersave = 1;

module_param_named(powersave, i915_powersave, int, 0600);



unsigned int i915_semaphores = 1;

module_param_named(semaphores, i915_semaphores, int, 0600);



unsigned int i915_enable_rc6 = 0;

module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
@@ -260,7 +263,7 @@ void intel_detect_pch (struct drm_device *dev) 
	}

}



void __gen6_force_wake_get(struct drm_i915_private *dev_priv)

void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	int count;
@@ -276,12 +279,22 @@ void __gen6_force_wake_get(struct drm_i915_private *dev_priv) 
		udelay(10);

}



void __gen6_force_wake_put(struct drm_i915_private *dev_priv)

void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE, 0);

	POSTING_READ(FORCEWAKE);

}



void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)

{

	int loop = 500;

	u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

	while (fifo < 20 && loop--) {

		udelay(10);

		fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);

	}

}



static int i915_drm_freeze(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

drivers/gpu/drm/i915/i915_drv.h

+18 −5
Original line number Diff line number Diff line
@@ -961,6 +961,7 @@ extern int i915_max_ioctl; 
extern unsigned int i915_fbpercrtc;

extern int i915_panel_ignore_lid;

extern unsigned int i915_powersave;

extern unsigned int i915_semaphores;

extern unsigned int i915_lvds_downclock;

extern unsigned int i915_panel_use_ssc;

extern int i915_vbt_sdvo_panel_type;
@@ -1172,6 +1173,9 @@ void i915_gem_detach_phys_object(struct drm_device *dev, 
void i915_gem_free_all_phys_object(struct drm_device *dev);

void i915_gem_release(struct drm_device *dev, struct drm_file *file);



uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);



/* i915_gem_gtt.c */

void i915_gem_restore_gtt_mappings(struct drm_device *dev);

int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
@@ -1348,20 +1352,29 @@ __i915_write(64, q) 
 * must be set to prevent GT core from power down and stale values being

 * returned.

 */

void __gen6_force_wake_get(struct drm_i915_private *dev_priv);

void __gen6_force_wake_put (struct drm_i915_private *dev_priv);

static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)

void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);



static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)

{

	u32 val;



	if (dev_priv->info->gen >= 6) {

		__gen6_force_wake_get(dev_priv);

		__gen6_gt_force_wake_get(dev_priv);

		val = I915_READ(reg);

		__gen6_force_wake_put(dev_priv);

		__gen6_gt_force_wake_put(dev_priv);

	} else

		val = I915_READ(reg);



	return val;

}



static inline void i915_gt_write(struct drm_i915_private *dev_priv,

				u32 reg, u32 val)

{

	if (dev_priv->info->gen >= 6)

		__gen6_gt_wait_for_fifo(dev_priv);

	I915_WRITE(reg, val);

}

#endif

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -1404,7 +1404,7 @@ i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) 
 * Return the required GTT alignment for an object, only taking into account

 * unfenced tiled surface requirements.

 */

static uint32_t

uint32_t

i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)

{

	struct drm_device *dev = obj->base.dev;

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+2 −1
Original line number Diff line number Diff line
@@ -748,7 +748,8 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj, 
	if (from == NULL || to == from)

		return 0;



	if (INTEL_INFO(obj->base.dev)->gen < 6)

	/* XXX gpu semaphores are implicated in various hard hangs on SNB */

	if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)

		return i915_gem_object_wait_rendering(obj);



	idx = intel_ring_sync_index(from, to);