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Commit 47a1e0fe authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvd0/dmaobj: initial bind() method implementation 



Currently unused, and rudimentary.  Lots to figure out here still, but
this is sufficient for what disp will need.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 80fe155b

drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c

+34 −1
Original line number Diff line number Diff line
@@ -39,7 +39,8 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, 
		 struct nouveau_dmaobj *dmaobj,

		 struct nouveau_gpuobj **pgpuobj)

{

	int ret = 0;

	u32 flags0 = 0x00000000;

	int ret;



	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {

		switch (nv_mclass(parent->parent)) {
@@ -50,6 +51,38 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, 
	} else

		return 0;



	if (!(dmaobj->conf0 & NVD0_DMA_CONF0_ENABLE)) {

		if (dmaobj->target == NV_MEM_TARGET_VM) {

			dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_VM;

			dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_LP;

		} else {

			dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR;

			dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_SP;

		}

	}



	flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_TYPE) << 20;

	flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_PAGE) >> 4;



	switch (dmaobj->target) {

	case NV_MEM_TARGET_VRAM:

		flags0 |= 0x00000009;

		break;

	default:

		return -EINVAL;

		break;

	}



	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);

	if (ret == 0) {

		nv_wo32(*pgpuobj, 0x00, flags0);

		nv_wo32(*pgpuobj, 0x04, dmaobj->start >> 8);

		nv_wo32(*pgpuobj, 0x08, dmaobj->limit >> 8);

		nv_wo32(*pgpuobj, 0x0c, 0x00000000);

		nv_wo32(*pgpuobj, 0x10, 0x00000000);

		nv_wo32(*pgpuobj, 0x14, 0x00000000);

	}



	return ret;

}

drivers/gpu/drm/nouveau/core/include/core/class.h

+9 −0
Original line number Diff line number Diff line
@@ -80,6 +80,15 @@ struct nv_device_class { 
#define NVC0_DMA_CONF0_TYPE_LINEAR                                   0x00000000

#define NVC0_DMA_CONF0_TYPE_VM                                       0x000000ff



/* NVD9- */

#define NVD0_DMA_CONF0_ENABLE                                        0x80000000

#define NVD0_DMA_CONF0_PAGE                                          0x00000400

#define NVD0_DMA_CONF0_PAGE_LP                                       0x00000000

#define NVD0_DMA_CONF0_PAGE_SP                                       0x00000400

#define NVD0_DMA_CONF0_TYPE                                          0x000000ff

#define NVD0_DMA_CONF0_TYPE_LINEAR                                   0x00000000

#define NVD0_DMA_CONF0_TYPE_VM                                       0x000000ff



struct nv_dma_class {

	u32 flags;

	u32 pad0;