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Commit 4790ecfa authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sun7i: Add Allwinner A20 DTSI 



The Allwinner A20 SoC is based on 2 Cortex A7, an ARM Mali GPU, and is
built to be pin-compatible with the older Allwinner A10.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 0bef900b

arch/arm/boot/dts/sun7i-a20.dtsi

0 → 100644
+172 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/include/ "skeleton.dtsi"



/ {

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <0>;

		};



		cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

		};

	};



	memory {

		reg = <0x40000000 0x80000000>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		osc24M: osc24M@01c20050 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

		};



		osc32k: osc32k {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

		};

	};



	soc@01c00000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		timer@01c20c00 {

			compatible = "allwinner,sun4i-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <0 22 1>,

				     <0 23 1>,

				     <0 24 1>,

				     <0 25 1>,

				     <0 67 1>,

				     <0 68 1>;

			clocks = <&osc24M>;

		};



		wdt: watchdog@01c20c90 {

			compatible = "allwinner,sun4i-wdt";

			reg = <0x01c20c90 0x10>;

		};



		uart0: serial@01c28000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28000 0x400>;

			interrupts = <0 1 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <0 2 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <0 3 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <0 4 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart4: serial@01c29000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29000 0x400>;

			interrupts = <0 17 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart5: serial@01c29400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29400 0x400>;

			interrupts = <0 18 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart6: serial@01c29800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29800 0x400>;

			interrupts = <0 19 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart7: serial@01c29c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29c00 0x400>;

			interrupts = <0 20 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		gic: interrupt-controller@01c81000 {

			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";

			reg = <0x01c81000 0x1000>,

			      <0x01c82000 0x1000>,

			      <0x01c84000 0x2000>,

			      <0x01c86000 0x2000>;

			interrupt-controller;

			#interrupt-cells = <3>;

			interrupts = <1 9 0xf04>;

		};

	};

};