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Commit 47573d76 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add device tree support for msm8953"

parents 6b845a99 3cac2785
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+5 −0
Original line number Diff line number Diff line
@@ -153,6 +153,11 @@ dtb-$(CONFIG_ARCH_SDM670) += sdm670-rumi.dtb \
	qcs605-external-codec-mtp.dtb
endif

ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
else
dtb-$(CONFIG_ARCH_MSM8953) += msm8953-mtp.dtb
endif

always		:= $(dtb-y)
subdir-y	:= $(dts-dirs)
clean-files	:= *.dtb
+283 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/ {
	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
				core2 {
					cpu = <&CPU2>;
				};
				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
				core2 {
					cpu = <&CPU6>;
				};
				core3 {
					cpu = <&CPU7>;
				};
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0>;
			enable-method = "psci";
			efficiency = <1024>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      /* A53 L2 dump not supported */
			      qcom,dump-size = <0x0>;
			};
			L1_I_0: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_0: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x1>;
			efficiency = <1024>;
			next-level-cache = <&L2_0>;
			L1_I_1: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_1: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x2>;
			efficiency = <1024>;
			next-level-cache = <&L2_0>;
			L1_I_2: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_2: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x3>;
			efficiency = <1024>;
			next-level-cache = <&L2_0>;
			L1_I_3: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_3: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x100>;
			efficiency = <1126>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      /* A53 L2 dump not supported */
			      qcom,dump-size = <0x0>;
			};
			L1_I_100: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_100: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x101>;
			efficiency = <1126>;
			next-level-cache = <&L2_1>;
			L1_I_101: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_101: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x102>;
			efficiency = <1126>;
			next-level-cache = <&L2_1>;
			L1_I_102: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_102: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			enable-method = "psci";
			reg = <0x103>;
			efficiency = <1126>;
			next-level-cache = <&L2_1>;
			L1_I_103: l1-icache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x8800>;
			};
			L1_D_103: l1-dcache {
			      compatible = "arm,arch-cache";
			      qcom,dump-size = <0x9000>;
			};
		};
	};
};

&soc {
	cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l2_dump0 {
			/* L2 cache dump for A53 cluster */
			qcom,dump-node = <&L2_0>;
			qcom,dump-id = <0xC0>;
		};
		qcom,l2_dump1 {
			/* L2 cache dump for A53 cluster */
			qcom,dump-node = <&L2_1>;
			qcom,dump-id = <0xC1>;
		};
		qcom,l1_i_cache0 {
			qcom,dump-node = <&L1_I_0>;
			qcom,dump-id = <0x60>;
		};
		qcom,l1_i_cache1 {
			qcom,dump-node = <&L1_I_1>;
			qcom,dump-id = <0x61>;
		};
		qcom,l1_i_cache2 {
			qcom,dump-node = <&L1_I_2>;
			qcom,dump-id = <0x62>;
		};
		qcom,l1_i_cache3 {
			qcom,dump-node = <&L1_I_3>;
			qcom,dump-id = <0x63>;
		};
		qcom,l1_i_cache100 {
			qcom,dump-node = <&L1_I_100>;
			qcom,dump-id = <0x64>;
		};
		qcom,l1_i_cache101 {
			qcom,dump-node = <&L1_I_101>;
			qcom,dump-id = <0x65>;
		};
		qcom,l1_i_cache102 {
			qcom,dump-node = <&L1_I_102>;
			qcom,dump-id = <0x66>;
		};
		qcom,l1_i_cache103 {
			qcom,dump-node = <&L1_I_103>;
			qcom,dump-id = <0x67>;
		};
		qcom,l1_d_cache0 {
			qcom,dump-node = <&L1_D_0>;
			qcom,dump-id = <0x80>;
		};
		qcom,l1_d_cache1 {
			qcom,dump-node = <&L1_D_1>;
			qcom,dump-id = <0x81>;
		};
		qcom,l1_d_cache2 {
			qcom,dump-node = <&L1_D_2>;
			qcom,dump-id = <0x82>;
		};
		qcom,l1_d_cache3 {
			qcom,dump-node = <&L1_D_3>;
			qcom,dump-id = <0x83>;
		};
		qcom,l1_d_cache100 {
			qcom,dump-node = <&L1_D_100>;
			qcom,dump-id = <0x84>;
		};
		qcom,l1_d_cache101 {
			qcom,dump-node = <&L1_D_101>;
			qcom,dump-id = <0x85>;
		};
		qcom,l1_d_cache102 {
			qcom,dump-node = <&L1_D_102>;
			qcom,dump-id = <0x86>;
		};
		qcom,l1_d_cache103 {
			qcom,dump-node = <&L1_D_103>;
			qcom,dump-id = <0x87>;
		};
	};
};
+24 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "msm8953.dtsi"
#include "msm8953-mtp.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. MSM8953 + PMI8950 MTP";
	compatible = "qcom,msm8953-mtp", "qcom,msm8953", "qcom,mtp";
	qcom,board-id= <8 0>;
	qcom,pmic-id = <0x010016 0x010011 0x0 0x0>;
};
+18 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&blsp1_uart0 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_active>;
};
+1506 −0

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