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Commit 474aa3dd authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-core-4.9' of git://git.infradead.org/users/jcooper/linux into irq/core 

Pull irqchip core changes for v4.9 from Jason Cooper

 - jcore: Add AIC driver
 - mips-gic: Use for_each_set_bit
 - mvebu: Add PIC driver
parents 5a79d596 f61f8606

Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

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J-Core Advanced Interrupt Controller



Required properties:



- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic

  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for

  the "aic2" core with 64 interrupts.



- reg: Memory region(s) for configuration. For SMP, there should be one

  region per cpu, indexed by the sequential, zero-based hardware cpu

  number.



- interrupt-controller: Identifies the node as an interrupt controller



- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.





Example:



aic: interrupt-controller@200 {

	compatible = "jcore,aic2";

	reg = < 0x200 0x30 0x500 0x30 >;

	interrupt-controller;

	#interrupt-cells = <1>;

};

Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt

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Marvell Armada 7K/8K PIC Interrupt controller

---------------------------------------------



This is the Device Tree binding for the PIC, a secondary interrupt

controller available on the Marvell Armada 7K/8K ARM64 SoCs, and

typically connected to the GIC as the primary interrupt controller.



Required properties:

- compatible: should be "marvell,armada-8k-pic"

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: the number of cells to define interrupts on this

  controller. Should be 1

- reg: the register area for the PIC interrupt controller

- interrupts: the interrupt to the primary interrupt controller,

  typically the GIC



Example:



	pic: interrupt-controller@3f0100 {

		compatible = "marvell,armada-8k-pic";

		reg = <0x3f0100 0x10>;

		#interrupt-cells = <1>;

		interrupt-controller;

		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;

	};

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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@@ -31,7 +31,7 @@ Required properties: 
Example:



	odmi: odmi@300000 {

		compatible = "marvell,ap806-odm-controller",

		compatible = "marvell,ap806-odmi-controller",

			     "marvell,odmi-controller";

		interrupt-controller;

		msi-controller;

arch/arm64/Kconfig.platforms

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@@ -93,6 +93,7 @@ config ARCH_MVEBU 
	select ARMADA_CP110_SYSCON

	select ARMADA_37XX_CLK

	select MVEBU_ODMI

	select MVEBU_PIC

	help

	  This enables support for Marvell EBU familly, including:

	   - Armada 3700 SoC Family

drivers/irqchip/Kconfig

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@@ -157,6 +157,13 @@ config PIC32_EVIC 
	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN



config JCORE_AIC

	bool "J-Core integrated AIC"

	depends on OF && (SUPERH || COMPILE_TEST)

	select IRQ_DOMAIN

	help

	  Support for the J-Core integrated AIC.



config RENESAS_INTC_IRQPIN

	bool

	select IRQ_DOMAIN
@@ -252,6 +259,9 @@ config IRQ_MXS 
config MVEBU_ODMI

	bool



config MVEBU_PIC

	bool



config LS_SCFG_MSI

	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE

	depends on PCI && PCI_MSI