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Commit 4702d599 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'xgene-dts-for-v4.5-v1' of https://github.com/AppliedMicro/xgene-next into next/dt64 

Merge "DTS changes for X-Gene platforms queued for v4.5" from Duc Dang

This patch set adds DTS entries to support various IPs
for X-Gene v1 and X-Gene v2 SoC:
- X-Gene v1: Enable support for MMC, USB, GPIO controllers,
  I2C controller, L2 Cache topology
- X-Gene v2: Enable support for MMC, USB, GPIO controller,
  I2C controller (with RTC), PCIe controller with GICv2m MSI,
  EDAC, L2 Cache topology, TRNG

* tag 'xgene-dts-for-v4.5-v1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: Add L2 cache topology for APM X-Gene SoC
  arm64: dts: Add RTC DTS entry for X-Gene v2 SoC platform
  arm64: dts: Add Designware I2C controller DTS entries for X-Gene v2 SoC platform
  arm64: dts: Add Designware I2C controller DTS entries for X-Gene v1 SoC
  arm64: dts: Add APM X-Gene v2 SoC EDAC DTS entries
  arm64: dts: Add APM X-Gene v2 SoC Designware GPIO controller DTS entry
  arm64: dts: Add Designware GPIO dts binding for APM X-Gene v1 platform
  arm64: dts: Add APM X-Gene v2 SoC GFC GPIO controller DTS entry
  arm64: dts: Add APM X-Gene v1 SoC GFC GPIO controller DTS entries
  arm64: dts: Add USB nodes for APM X-Gene v2 platforms
  arm64: dts: Add USB nodes for APM X-Gene v1 platforms
  arm64: dts: Add PCIe node for APM X-Gene v2 platforms
  arm64: dts: Add v2m MSI frame nodes for APM X-Gene v2 platforms
  arm64: dts: Add RNG device tree nodes for APM X-Gene v2 platform
  arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block
  arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC
  arm64: dts: Add the arasan mmc DTS entries for APM X-Gene v1 SoC
parents fd0adfd8 8000bc3f

arch/arm64/boot/dts/apm/apm-merlin.dts

+12 −0
Original line number Diff line number Diff line
@@ -70,3 +70,15 @@ 
&xgenet1 {

	status = "ok";

};



&mmc0 {

	status = "ok";

};



&i2c4 {

	rtc68: rtc@68 {

		compatible = "dallas,ds1337";

		reg = <0x68>;

		status = "ok";

	};

};

arch/arm64/boot/dts/apm/apm-mustang.dts

+4 −0
Original line number Diff line number Diff line
@@ -74,3 +74,7 @@ 
&xgenet {

	status = "ok";

};



&mmc0 {

	status = "ok";

};

arch/arm64/boot/dts/apm/apm-shadowcat.dtsi

+401 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
			reg = <0x0 0x000>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_0>;

		};

		cpu@001 {

			device_type = "cpu";
@@ -32,6 +33,7 @@ 
			reg = <0x0 0x001>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_0>;

		};

		cpu@100 {

			device_type = "cpu";
@@ -39,6 +41,7 @@ 
			reg = <0x0 0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_1>;

		};

		cpu@101 {

			device_type = "cpu";
@@ -46,6 +49,7 @@ 
			reg = <0x0 0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_1>;

		};

		cpu@200 {

			device_type = "cpu";
@@ -53,6 +57,7 @@ 
			reg = <0x0 0x200>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_2>;

		};

		cpu@201 {

			device_type = "cpu";
@@ -60,6 +65,7 @@ 
			reg = <0x0 0x201>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_2>;

		};

		cpu@300 {

			device_type = "cpu";
@@ -67,6 +73,7 @@ 
			reg = <0x0 0x300>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_3>;

		};

		cpu@301 {

			device_type = "cpu";
@@ -74,6 +81,19 @@ 
			reg = <0x0 0x301>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_3>;

		};

		xgene_L2_0: l2-cache-0 {

			compatible = "cache";

		};

		xgene_L2_1: l2-cache-1 {

			compatible = "cache";

		};

		xgene_L2_2: l2-cache-2 {

			compatible = "cache";

		};

		xgene_L2_3: l2-cache-3 {

			compatible = "cache";

		};

	};
@@ -89,6 +109,86 @@ 
		      <0x0 0x780A0000 0x0 0x20000>,	/* GIC CPU */

		      <0x0 0x780C0000 0x0 0x10000>,	/* GIC VCPU Control */

		      <0x0 0x780E0000 0x0 0x20000>;	/* GIC VCPU */

		v2m0: v2m@0x00000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x0 0x0 0x1000>;

		};

		v2m1: v2m@0x10000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x10000 0x0 0x1000>;

		};

		v2m2: v2m@0x20000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x20000 0x0 0x1000>;

		};

		v2m3: v2m@0x30000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x30000 0x0 0x1000>;

		};

		v2m4: v2m@0x40000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x40000 0x0 0x1000>;

		};

		v2m5: v2m@0x50000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x50000 0x0 0x1000>;

		};

		v2m6: v2m@0x60000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x60000 0x0 0x1000>;

		};

		v2m7: v2m@0x70000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x70000 0x0 0x1000>;

		};

		v2m8: v2m@0x80000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x80000 0x0 0x1000>;

		};

		v2m9: v2m@0x90000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0x90000 0x0 0x1000>;

		};

		v2m10: v2m@0xA0000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0xA0000 0x0 0x1000>;

		};

		v2m11: v2m@0xB0000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0xB0000 0x0 0x1000>;

		};

		v2m12: v2m@0xC0000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0xC0000 0x0 0x1000>;

		};

		v2m13: v2m@0xD0000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0xD0000 0x0 0x1000>;

		};

		v2m14: v2m@0xE0000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0xE0000 0x0 0x1000>;

		};

		v2m15: v2m@0xF0000 {

			compatible = "arm,gic-v2m-frame";

			msi-controller;

			reg = <0x0 0xF0000 0x0 0x1000>;

		};

	};



	pmu {
@@ -140,6 +240,47 @@ 
				clock-output-names = "socplldiv2";

			};



			ahbclk: ahbclk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "div-reg";

				divider-offset = <0x164>;

				divider-width = <0x5>;

				divider-shift = <0x0>;

				clock-output-names = "ahbclk";

			};



			sbapbclk: sbapbclk@1704c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&ahbclk 0>;

				reg = <0x0 0x1704c000 0x0 0x2000>;

				reg-names = "div-reg";

				divider-offset = <0x10>;

				divider-width = <0x2>;

				divider-shift = <0x0>;

				clock-output-names = "sbapbclk";

			};



			sdioclk: sdioclk@1f2ac000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2ac000 0x0 0x1000

					0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg", "div-reg";

				csr-offset = <0x0>;

				csr-mask = <0x2>;

				enable-offset = <0x8>;

				enable-mask = <0x2>;

				divider-offset = <0x178>;

				divider-width = <0x8>;

				divider-shift = <0x0>;

				clock-output-names = "sdioclk";

			};



			pcie0clk: pcie0clk@1f2bc000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;
@@ -149,6 +290,15 @@ 
				clock-output-names = "pcie0clk";

			};



			pcie1clk: pcie1clk@1f2cc000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2cc000 0x0 0x1000>;

				reg-names = "csr-reg";

				clock-output-names = "pcie1clk";

			};



			xge0clk: xge0clk@1f61c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;
@@ -170,6 +320,45 @@ 
				csr-mask = <0x3>;

				clock-output-names = "xge1clk";

			};



			rngpkaclk: rngpkaclk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg";

				csr-offset = <0xc>;

				csr-mask = <0x10>;

				enable-offset = <0x10>;

				enable-mask = <0x10>;

				clock-output-names = "rngpkaclk";

			};



			i2c1clk: i2c1clk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&sbapbclk 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg";

				csr-offset = <0xc>;

				csr-mask = <0x4>;

				enable-offset = <0x10>;

				enable-mask = <0x4>;

				clock-output-names = "i2c1clk";

			};



			i2c4clk: i2c4clk@1704c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&sbapbclk 0>;

				reg = <0x0 0x1704c000 0x0 0x1000>;

				reg-names = "csr-reg";

				csr-offset = <0x0>;

				csr-mask = <0x40>;

				enable-offset = <0x8>;

				enable-mask = <0x40>;

				clock-output-names = "i2c4clk";

			};

		};



		scu: system-clk-controller@17000000 {
@@ -184,6 +373,99 @@ 
			mask = <0x1>;

		};



		csw: csw@7e200000 {

			compatible = "apm,xgene-csw", "syscon";

			reg = <0x0 0x7e200000 0x0 0x1000>;

		};



		mcba: mcba@7e700000 {

			compatible = "apm,xgene-mcb", "syscon";

			reg = <0x0 0x7e700000 0x0 0x1000>;

		};



		mcbb: mcbb@7e720000 {

			compatible = "apm,xgene-mcb", "syscon";

			reg = <0x0 0x7e720000 0x0 0x1000>;

		};



		efuse: efuse@1054a000 {

			compatible = "apm,xgene-efuse", "syscon";

			reg = <0x0 0x1054a000 0x0 0x20>;

		};



		edac@78800000 {

			compatible = "apm,xgene-edac";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			regmap-csw = <&csw>;

			regmap-mcba = <&mcba>;

			regmap-mcbb = <&mcbb>;

			regmap-efuse = <&efuse>;

			reg = <0x0 0x78800000 0x0 0x100>;

			interrupts = <0x0 0x20 0x4>,

				     <0x0 0x21 0x4>,

				     <0x0 0x27 0x4>;



			edacmc@7e800000 {

				compatible = "apm,xgene-edac-mc";

				reg = <0x0 0x7e800000 0x0 0x1000>;

				memory-controller = <0>;

			};



			edacmc@7e840000 {

				compatible = "apm,xgene-edac-mc";

				reg = <0x0 0x7e840000 0x0 0x1000>;

				memory-controller = <1>;

			};



			edacmc@7e880000 {

				compatible = "apm,xgene-edac-mc";

				reg = <0x0 0x7e880000 0x0 0x1000>;

				memory-controller = <2>;

			};



			edacmc@7e8c0000 {

				compatible = "apm,xgene-edac-mc";

				reg = <0x0 0x7e8c0000 0x0 0x1000>;

				memory-controller = <3>;

			};



			edacpmd@7c000000 {

				compatible = "apm,xgene-edac-pmd";

				reg = <0x0 0x7c000000 0x0 0x200000>;

				pmd-controller = <0>;

			};



			edacpmd@7c200000 {

				compatible = "apm,xgene-edac-pmd";

				reg = <0x0 0x7c200000 0x0 0x200000>;

				pmd-controller = <1>;

			};



			edacpmd@7c400000 {

				compatible = "apm,xgene-edac-pmd";

				reg = <0x0 0x7c400000 0x0 0x200000>;

				pmd-controller = <2>;

			};



			edacpmd@7c600000 {

				compatible = "apm,xgene-edac-pmd";

				reg = <0x0 0x7c600000 0x0 0x200000>;

				pmd-controller = <3>;

			};



			edacl3@7e600000 {

				compatible = "apm,xgene-edac-l3-v2";

				reg = <0x0 0x7e600000 0x0 0x1000>;

			};



			edacsoc@7e930000 {

				compatible = "apm,xgene-edac-soc";

				reg = <0x0 0x7e930000 0x0 0x1000>;

			};

		};



		serial0: serial@10600000 {

			device_type = "serial";

			compatible = "ns16550";
@@ -194,6 +476,65 @@ 
			interrupts = <0x0 0x4c 0x4>;

		};



		usb0: dwusb@19000000 {

			status = "disabled";

			compatible = "snps,dwc3";

			reg =  <0x0 0x19000000 0x0 0x100000>;

			interrupts = <0x0 0x5d 0x4>;

			dma-coherent;

			dr_mode = "host";

		};



		pcie0: pcie@1f2b0000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-pcie", "apm,xgene2-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */

				0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io */

				  0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000   /* mem */

				  0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;

			dma-coherent;

			clocks = <&pcie0clk 0>;

			msi-parent = <&v2m0>;

		};



		pcie1: pcie@1f2c0000 {

			status = "disabled";

			device_type = "pci";

			compatible = "apm,xgene-pcie", "apm,xgene2-pcie";

			#interrupt-cells = <1>;

			#size-cells = <2>;

			#address-cells = <3>;

			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */

				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */

			reg-names = "csr", "cfg";

			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io */

				  0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000   /* mem */

				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */

			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000

				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;

			interrupt-map-mask = <0x0 0x0 0x0 0x7>;

			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1

					 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1

					 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1

					 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;

			dma-coherent;

			clocks = <&pcie1clk 0>;

			msi-parent = <&v2m0>;

		};



		sata1: sata@1a000000 {

			compatible = "apm,xgene-ahci";

			reg = <0x0 0x1a000000 0x0 0x1000>,
@@ -224,6 +565,38 @@ 
			dma-coherent;

		};



		mmc0: mmc@1c000000 {

			compatible = "arasan,sdhci-4.9a";

			reg = <0x0 0x1c000000 0x0 0x100>;

			interrupts = <0x0 0x49 0x4>;

			dma-coherent;

			no-1-8-v;

			clock-names = "clk_xin", "clk_ahb";

			clocks = <&sdioclk 0>, <&ahbclk 0>;

		};



		gfcgpio: gfcgpio@1f63c000 {

			compatible = "apm,xgene-gpio";

			reg = <0x0 0x1f63c000 0x0 0x40>;

			gpio-controller;

			#gpio-cells = <2>;

		};



		dwgpio: dwgpio@1c024000 {

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x1c024000 0x0 0x1000>;

			reg-io-width = <4>;

			#address-cells = <1>;

			#size-cells = <0>;



			porta: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				snps,nr-gpios = <32>;

				reg = <0>;

			};

		};



		sbgpio: sbgpio@17001000{

			compatible = "apm,xgene-gpio-sb";

			reg = <0x0 0x17001000 0x0 0x400>;
@@ -267,5 +640,33 @@ 
			local-mac-address = [00 01 73 00 00 02];

			phy-connection-type = "xgmii";

		};



		rng: rng@10520000 {

			compatible = "apm,xgene-rng";

			reg = <0x0 0x10520000 0x0 0x100>;

			interrupts = <0x0 0x41 0x4>;

			clocks = <&rngpkaclk 0>;

		};



		i2c1: i2c1@10511000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0x0 0x10511000 0x0 0x1000>;

			interrupts = <0 0x45 0x4>;

			#clock-cells = <1>;

			clocks = <&i2c1clk 0>;

			bus_num = <1>;

		};



		i2c4: i2c4@10640000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0x0 0x10640000 0x0 0x1000>;

			interrupts = <0 0x3A 0x4>;

			clocks = <&i2c4clk 0>;

			bus_num = <4>;

		};

	};

};

arch/arm64/boot/dts/apm/apm-storm.dtsi

+126 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
			reg = <0x0 0x000>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_0>;

		};

		cpu@001 {

			device_type = "cpu";
@@ -32,6 +33,7 @@ 
			reg = <0x0 0x001>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_0>;

		};

		cpu@100 {

			device_type = "cpu";
@@ -39,6 +41,7 @@ 
			reg = <0x0 0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_1>;

		};

		cpu@101 {

			device_type = "cpu";
@@ -46,6 +49,7 @@ 
			reg = <0x0 0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_1>;

		};

		cpu@200 {

			device_type = "cpu";
@@ -53,6 +57,7 @@ 
			reg = <0x0 0x200>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_2>;

		};

		cpu@201 {

			device_type = "cpu";
@@ -60,6 +65,7 @@ 
			reg = <0x0 0x201>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_2>;

		};

		cpu@300 {

			device_type = "cpu";
@@ -67,6 +73,7 @@ 
			reg = <0x0 0x300>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_3>;

		};

		cpu@301 {

			device_type = "cpu";
@@ -74,6 +81,19 @@ 
			reg = <0x0 0x301>;

			enable-method = "spin-table";

			cpu-release-addr = <0x1 0x0000fff8>;

			next-level-cache = <&xgene_L2_3>;

		};

		xgene_L2_0: l2-cache-0 {

			compatible = "cache";

		};

		xgene_L2_1: l2-cache-1 {

			compatible = "cache";

		};

		xgene_L2_2: l2-cache-2 {

			compatible = "cache";

		};

		xgene_L2_3: l2-cache-3 {

			compatible = "cache";

		};

	};
@@ -150,6 +170,35 @@ 
				clock-output-names = "socplldiv2";

			};



			ahbclk: ahbclk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "div-reg";

				divider-offset = <0x164>;

				divider-width = <0x5>;

				divider-shift = <0x0>;

				clock-output-names = "ahbclk";

			};



			sdioclk: sdioclk@1f2ac000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2ac000 0x0 0x1000

					0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg", "div-reg";

				csr-offset = <0x0>;

				csr-mask = <0x2>;

				enable-offset = <0x8>;

				enable-mask = <0x2>;

				divider-offset = <0x178>;

				divider-width = <0x8>;

				divider-shift = <0x0>;

				clock-output-names = "sdioclk";

			};



			qmlclk: qmlclk {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;
@@ -388,6 +437,20 @@ 
				reg-names = "csr-reg";

				clock-output-names = "dmaclk";

			};



			i2cclk: i2cclk@17000000 {

				status = "disabled";

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&ahbclk 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg";

				csr-offset = <0xc>;

				csr-mask = <0x4>;

				enable-offset = <0x10>;

				enable-mask = <0x4>;

				clock-output-names = "i2cclk";

			};

		};



		msi: msi@79000000 {
@@ -686,6 +749,50 @@ 
			interrupts = <0x0 0x4f 0x4>;

		};



		mmc0: mmc@1c000000 {

			compatible = "arasan,sdhci-4.9a";

			reg = <0x0 0x1c000000 0x0 0x100>;

			interrupts = <0x0 0x49 0x4>;

			dma-coherent;

			no-1-8-v;

			clock-names = "clk_xin", "clk_ahb";

			clocks = <&sdioclk 0>, <&ahbclk 0>;

		};



		gfcgpio: gfcgpio0@1701c000 {

			compatible = "apm,xgene-gpio";

			reg = <0x0 0x1701c000 0x0 0x40>;

			gpio-controller;

			#gpio-cells = <2>;

		};



		dwgpio: dwgpio@1c024000 {

			compatible = "snps,dw-apb-gpio";

			reg = <0x0 0x1c024000 0x0 0x1000>;

			reg-io-width = <4>;

			#address-cells = <1>;

			#size-cells = <0>;



			porta: gpio-controller@0 {

				compatible = "snps,dw-apb-gpio-port";

				gpio-controller;

				snps,nr-gpios = <32>;

				reg = <0>;

			};

		};



		i2c0: i2c0@10512000 {

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0x0 0x10512000 0x0 0x1000>;

			interrupts = <0 0x44 0x4>;

			#clock-cells = <1>;

			clocks = <&i2cclk 0>;

			bus_num = <0>;

		};



		phy1: phy@1f21a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f21a000 0x0 0x100>;
@@ -760,6 +867,25 @@ 
			phy-names = "sata-phy";

		};



		/* Do not change dwusb name, coded for backward compatibility */

		usb0: dwusb@19000000 {

			status = "disabled";

			compatible = "snps,dwc3";

			reg =  <0x0 0x19000000 0x0 0x100000>;

			interrupts = <0x0 0x89 0x4>;

			dma-coherent;

			dr_mode = "host";

		};



		usb1: dwusb@19800000 {

			status = "disabled";

			compatible = "snps,dwc3";

			reg =  <0x0 0x19800000 0x0 0x100000>;

			interrupts = <0x0 0x8a 0x4>;

			dma-coherent;

			dr_mode = "host";

		};



		sbgpio: sbgpio@17001000{

			compatible = "apm,xgene-gpio-sb";

			reg = <0x0 0x17001000 0x0 0x400>;