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Commit 46d7e4de authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add cooling device property to CPUs for sdm632 



Add cooling-cells property to CPUs of sdm632. This enables the CPU
cooling device to be referenced in a thermal zone definition.

Change-Id: If9891370b23449e281ab5df888f87ea3d0d65d46
Signed-off-by: default avatarManaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
parent b8a3da42

arch/arm64/boot/dts/qcom/sdm632-cpu.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ 
			efficiency = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			next-level-cache = <&L2_0>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -85,6 +86,7 @@ 
			efficiency = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			next-level-cache = <&L2_0>;

			#cooling-cells = <2>;

			L1_I_1: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9040>;
@@ -106,6 +108,7 @@ 
			efficiency = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			next-level-cache = <&L2_0>;

			#cooling-cells = <2>;

			L1_I_2: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9040>;
@@ -127,6 +130,7 @@ 
			efficiency = <1024>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;

			next-level-cache = <&L2_0>;

			#cooling-cells = <2>;

			L1_I_3: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x9040>;
@@ -148,6 +152,7 @@ 
			efficiency = <1638>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_1>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;
@@ -173,6 +178,7 @@ 
			efficiency = <1638>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_1>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_101: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x12000>;
@@ -194,6 +200,7 @@ 
			efficiency = <1638>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_1>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_102: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x12000>;
@@ -215,6 +222,7 @@ 
			efficiency = <1638>;

			sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_1>;

			next-level-cache = <&L2_1>;

			#cooling-cells = <2>;

			L1_I_103: l1-icache {

			      compatible = "arm,arch-cache";

			      qcom,dump-size = <0x12000>;