clk: msm: gcc: Add parent for gcc_oxili_timer_clk

For gcc_oxili_timer_clk clock, rate setting request of 19.2 MHz is
getting failed from KGSL driver so fixing the same by adding the
XO as a parent.

Change-Id: I2444e4df80336ca42c525e149fd96c18cfe43630
Signed-off-by: Amit Nischal <anischal@codeaurora.org>