Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 45b2e976 authored by Mitchel Humpherys's avatar Mitchel Humpherys Committed by Patrick Daly
Browse files

iommu/io-pgtable-arm: Support SMMU coherent page tables 



Some SMMUs can walk page tables in the CPU cache.  Enable this
behavior for SMMUs whose device tree node has the `coherent'
property set.

Change-Id: Icbb7a7eaf6c6e85c3ff4f981fe1dd1c3917228dc
Signed-off-by: default avatarMitchel Humpherys <mitchelh@codeaurora.org>
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent 2d5b6cf6

drivers/iommu/io-pgtable-arm.c

+8 −3
Original line number Diff line number Diff line
@@ -929,6 +929,11 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
		return NULL;



	/* TCR */

	if (cfg->iommu_dev && cfg->iommu_dev->archdata.dma_coherent)

		reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |

			(ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);

	else

		reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |

			(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) |

			(ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT);