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Commit 459cc2c6 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: sor: Add HDMI support 



The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add
HDMI support and name the debugfs node after the type of SOR. The SOR
introduced with Tegra124 is known simply as "sor", whereas the
additional SOR found on Tegra210 is known as "sor1".

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 3309ac83

Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

+1 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ of the following host1x client modules: 
    - "nvidia,tegra124-sor": for Tegra124 and Tegra132

    - "nvidia,tegra132-sor": for Tegra132

    - "nvidia,tegra210-sor": for Tegra210

    - "nvidia,tegra210-sor1": for Tegra210

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain an entry for each entry in clock-names.

drivers/gpu/drm/tegra/dc.h

+4 −0
Original line number Diff line number Diff line
@@ -128,6 +128,8 @@ 
#define DC_DISP_DISP_WIN_OPTIONS		0x402

#define HDMI_ENABLE	(1 << 30)

#define DSI_ENABLE	(1 << 29)

#define SOR1_TIMING_CYA	(1 << 27)

#define SOR1_ENABLE	(1 << 26)

#define SOR_ENABLE	(1 << 25)

#define CURSOR_ENABLE	(1 << 16)
@@ -247,9 +249,11 @@ 
#define BASE_COLOR_SIZE565     (6 << 0)

#define BASE_COLOR_SIZE332     (7 << 0)

#define BASE_COLOR_SIZE888     (8 << 0)

#define DITHER_CONTROL_MASK    (3 << 8)

#define DITHER_CONTROL_DISABLE (0 << 8)

#define DITHER_CONTROL_ORDERED (2 << 8)

#define DITHER_CONTROL_ERRDIFF (3 << 8)

#define BASE_COLOR_SIZE_MASK   (0xf << 0)

#define BASE_COLOR_SIZE_666    (0 << 0)

#define BASE_COLOR_SIZE_111    (1 << 0)

#define BASE_COLOR_SIZE_222    (2 << 0)

drivers/gpu/drm/tegra/drm.c

+1 −0
Original line number Diff line number Diff line
@@ -1061,6 +1061,7 @@ static const struct of_device_id host1x_drm_subdevs[] = { 
	{ .compatible = "nvidia,tegra210-dc", },

	{ .compatible = "nvidia,tegra210-dsi", },

	{ .compatible = "nvidia,tegra210-sor", },

	{ .compatible = "nvidia,tegra210-sor1", },

	{ /* sentinel */ }

};

drivers/gpu/drm/tegra/sor.c

+960 −34

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/tegra/sor.h

+86 −0
Original line number Diff line number Diff line
@@ -43,6 +43,12 @@ 
#define  SOR_STATE_ASY_OWNER(x)			(((x) & 0xf) << 0)



#define SOR_HEAD_STATE0(x) (0x05 + (x))

#define  SOR_HEAD_STATE_RANGECOMPRESS_MASK (0x1 << 3)

#define  SOR_HEAD_STATE_DYNRANGE_MASK (0x1 << 2)

#define  SOR_HEAD_STATE_DYNRANGE_VESA (0 << 2)

#define  SOR_HEAD_STATE_DYNRANGE_CEA (1 << 2)

#define  SOR_HEAD_STATE_COLORSPACE_MASK (0x3 << 0)

#define  SOR_HEAD_STATE_COLORSPACE_RGB (0 << 0)

#define SOR_HEAD_STATE1(x) (0x07 + (x))

#define SOR_HEAD_STATE2(x) (0x09 + (x))

#define SOR_HEAD_STATE3(x) (0x0b + (x))
@@ -96,7 +102,11 @@ 


#define SOR_PLL1 0x18

/* XXX: read-only bit? */

#define  SOR_PLL1_LOADADJ_MASK			(0xf << 20)

#define  SOR_PLL1_LOADADJ(x)			(((x) & 0xf) << 20)

#define  SOR_PLL1_TERM_COMPOUT			(1 << 15)

#define  SOR_PLL1_TMDS_TERMADJ_MASK		(0xf << 9)

#define  SOR_PLL1_TMDS_TERMADJ(x)		(((x) & 0xf) << 9)

#define  SOR_PLL1_TMDS_TERM			(1 << 8)



#define SOR_PLL2 0x19
@@ -106,12 +116,17 @@ 
#define  SOR_PLL2_BANDGAP_POWERDOWN		(1 << 22)

#define  SOR_PLL2_POWERDOWN_OVERRIDE		(1 << 18)

#define  SOR_PLL2_SEQ_PLLCAPPD			(1 << 17)

#define  SOR_PLL2_SEQ_PLL_PULLDOWN		(1 << 16)



#define SOR_PLL3 0x1a

#define  SOR_PLL3_BG_VREF_LEVEL_MASK		(0xf << 24)

#define  SOR_PLL3_BG_VREF_LEVEL(x)		(((x) & 0xf) << 24)

#define  SOR_PLL3_PLL_VDD_MODE_1V8		(0 << 13)

#define  SOR_PLL3_PLL_VDD_MODE_3V3		(1 << 13)



#define SOR_CSTM 0x1b

#define  SOR_CSTM_ROTCLK_MASK			(0xf << 24)

#define  SOR_CSTM_ROTCLK(x)			(((x) & 0xf) << 24)

#define  SOR_CSTM_LVDS				(1 << 16)

#define  SOR_CSTM_LINK_ACT_B			(1 << 15)

#define  SOR_CSTM_LINK_ACT_A			(1 << 14)
@@ -124,15 +139,45 @@ 
#define SOR_CRCB 0x1e

#define SOR_BLANK 0x1f

#define SOR_SEQ_CTL 0x20

#define  SOR_SEQ_CTL_PD_PC_ALT(x)	(((x) & 0xf) << 12)

#define  SOR_SEQ_CTL_PD_PC(x)		(((x) & 0xf) <<  8)

#define  SOR_SEQ_CTL_PU_PC_ALT(x)	(((x) & 0xf) <<  4)

#define  SOR_SEQ_CTL_PU_PC(x)		(((x) & 0xf) <<  0)



#define SOR_LANE_SEQ_CTL 0x21

#define  SOR_LANE_SEQ_CTL_TRIGGER		(1 << 31)

#define  SOR_LANE_SEQ_CTL_STATE_BUSY		(1 << 28)

#define  SOR_LANE_SEQ_CTL_SEQUENCE_UP		(0 << 20)

#define  SOR_LANE_SEQ_CTL_SEQUENCE_DOWN		(1 << 20)

#define  SOR_LANE_SEQ_CTL_POWER_STATE_UP	(0 << 16)

#define  SOR_LANE_SEQ_CTL_POWER_STATE_DOWN	(1 << 16)

#define  SOR_LANE_SEQ_CTL_DELAY(x)		(((x) & 0xf) << 12)



#define SOR_SEQ_INST(x) (0x22 + (x))

#define  SOR_SEQ_INST_PLL_PULLDOWN (1 << 31)

#define  SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)

#define  SOR_SEQ_INST_ASSERT_PLL_RESET (1 << 29)

#define  SOR_SEQ_INST_BLANK_V (1 << 28)

#define  SOR_SEQ_INST_BLANK_H (1 << 27)

#define  SOR_SEQ_INST_BLANK_DE (1 << 26)

#define  SOR_SEQ_INST_BLACK_DATA (1 << 25)

#define  SOR_SEQ_INST_TRISTATE_IOS (1 << 24)

#define  SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)

#define  SOR_SEQ_INST_PIN_B_LOW (0 << 22)

#define  SOR_SEQ_INST_PIN_B_HIGH (1 << 22)

#define  SOR_SEQ_INST_PIN_A_LOW (0 << 21)

#define  SOR_SEQ_INST_PIN_A_HIGH (1 << 21)

#define  SOR_SEQ_INST_SEQUENCE_UP (0 << 19)

#define  SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19)

#define  SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18)

#define  SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18)

#define  SOR_SEQ_INST_PORT_POWERDOWN (1 << 17)

#define  SOR_SEQ_INST_PLL_POWERDOWN (1 << 16)

#define  SOR_SEQ_INST_HALT (1 << 15)

#define  SOR_SEQ_INST_WAIT_US (0 << 12)

#define  SOR_SEQ_INST_WAIT_MS (1 << 12)

#define  SOR_SEQ_INST_WAIT_VSYNC (2 << 12)

#define  SOR_SEQ_INST_WAIT(x) (((x) & 0x3ff) << 0)



#define SOR_PWM_DIV 0x32

#define  SOR_PWM_DIV_MASK			0xffffff
@@ -165,6 +210,10 @@ 
#define SOR_TRIG 0x48

#define SOR_MSCHECK 0x49

#define SOR_XBAR_CTRL 0x4a

#define  SOR_XBAR_CTRL_LINK1_XSEL(channel, value) ((((value) & 0x7) << ((channel) * 3)) << 17)

#define  SOR_XBAR_CTRL_LINK0_XSEL(channel, value) ((((value) & 0x7) << ((channel) * 3)) <<  2)

#define  SOR_XBAR_CTRL_LINK_SWAP (1 << 1)

#define  SOR_XBAR_CTRL_BYPASS (1 << 0)

#define SOR_XBAR_POL 0x4b



#define SOR_DP_LINKCTL0 0x4c
@@ -237,6 +286,7 @@ 
#define SOR_DP_DEBUG1 0x5f



#define SOR_DP_SPARE0 0x60

#define  SOR_DP_SPARE_DISP_VIDEO_PREAMBLE	(1 << 3)

#define  SOR_DP_SPARE_MACRO_SOR_CLK		(1 << 2)

#define  SOR_DP_SPARE_PANEL_INTERNAL		(1 << 1)

#define  SOR_DP_SPARE_SEQ_ENABLE		(1 << 0)
@@ -281,4 +331,40 @@ 
#define SOR_DP_LQ_CSTM1 0x70

#define SOR_DP_LQ_CSTM2 0x71



#define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a

#define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b

#define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c



#define SOR_HDMI_AVI_INFOFRAME_CTRL 0x9f

#define  INFOFRAME_CTRL_CHECKSUM_ENABLE	(1 << 9)

#define  INFOFRAME_CTRL_SINGLE		(1 << 8)

#define  INFOFRAME_CTRL_OTHER		(1 << 4)

#define  INFOFRAME_CTRL_ENABLE		(1 << 0)



#define SOR_HDMI_AVI_INFOFRAME_STATUS 0xa0

#define  INFOFRAME_STATUS_DONE		(1 << 0)



#define SOR_HDMI_AVI_INFOFRAME_HEADER 0xa1

#define  INFOFRAME_HEADER_LEN(x) (((x) & 0xff) << 16)

#define  INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)

#define  INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)



#define SOR_HDMI_CTRL 0xc0

#define  SOR_HDMI_CTRL_ENABLE (1 << 30)

#define  SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)

#define  SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 10)

#define  SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)



#define SOR_REFCLK 0xe6

#define  SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8)

#define  SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6)



#define SOR_INPUT_CONTROL 0xe8

#define  SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)

#define  SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x) (((x) & 0x1) << 0)



#define SOR_HDMI_VSI_INFOFRAME_CTRL 0x123

#define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124

#define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125



#endif