Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4526903a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

Main thing this time around is DSI support for msm8960/apq8064, which
should be helpful for getting an upstream kernel working on
nexus7/nexus4/etc.

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (29 commits)
  drm/msm/mdp: fix a problematic usage of WARN_ON()
  drm/msm/dsi: Added missing mutex_unlock
  drm/msm: ratelimit error irq msgs
  drm/msm: Use unlocked gem unreferencing
  drm/msm: trivial whitespace fix
  dt-bindings: msm/dsi: Add DSIv2 documentation
  dt-bindings: msm/dsi: Fix the order in which clocks are listed
  drm/msm/dsi: Enable MMSS SPFB port via syscon
  drm/msm/dsi: Don't use iommu for command TX buffer for DSIv2
  drm/msm/dsi: Add dsi_cfg for APQ8064
  drm/msm/dsi: Set up link clocks for DSIv2
  drm/msm/dsi: Parse bus clocks from a list
  drm/msm/dsi: Delay dsi_clk_init
  drm/msm/dsi: Use a better way to figure out DSI version
  drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY
  drm/msm/dsi: Add support for 28nm PHY on 8960
  drm/msm/dsi: Don't get byte/pixel source clocks from DT
  drm/msm/mdp4: Initialize DSI encoders
  drm/msm/mdp4: Call custom round_pixclk helper only if the encoder type is TMDS
  drm/msm/dsi: Add a mdp4 encoder for DSI
  ...
parents 663a233e 2abd1c88

Documentation/devicetree/bindings/display/msm/dsi.txt

+8 −4
Original line number Diff line number Diff line
@@ -14,17 +14,20 @@ Required properties: 
- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "mdp_core_clk"

  * "iface_clk"

  * "bus_clk"

  * "byte_clk"

  * "core_clk"

  * "core_mmss_clk"

  * "iface_clk"

  * "mdp_core_clk"

  * "byte_clk"

  * "pixel_clk"

  * "core_clk"

  For DSIv2, we need an additional clock:

   * "src_clk"

- vdd-supply: phandle to vdd regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vdda-supply: phandle to vdda regulator device node

- qcom,dsi-phy: phandle to DSI PHY device node

- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)



Optional properties:

- panel@0: Node of panel connected to this DSI controller.
@@ -51,6 +54,7 @@ Required properties: 
  * "qcom,dsi-phy-28nm-hpm"

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-28nm-8960"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

- reg-names: The names of register regions. The following regions are required:

Documentation/devicetree/bindings/display/msm/mdp.txt

+18 −8
Original line number Diff line number Diff line
@@ -2,18 +2,28 @@ Qualcomm adreno/snapdragon display controller 


Required properties:

- compatible:

  * "qcom,mdp" - mdp4

  * "qcom,mdp4" - mdp4

  * "qcom,mdp5" - mdp5

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the display controller.

- connectors: array of phandles for output device(s)

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

- clock-names: the following clocks are required.

  For MDP4:

   * "core_clk"

   * "iface_clk"

   * "lut_clk"

   * "src_clk"

   * "hdmi_clk"

  * "mpd_clk"

   * "mdp_clk"

  For MDP5:

   * "bus_clk"

   * "iface_clk"

   * "core_clk_src"

   * "core_clk"

   * "lut_clk" (some MDP5 versions may not need this)

   * "vsync_clk"



Optional properties:

- gpus: phandle for gpu device
@@ -26,7 +36,7 @@ Example: 
	...



	mdp: qcom,mdp@5100000 {

		compatible = "qcom,mdp";

		compatible = "qcom,mdp4";

		reg = <0x05100000 0xf0000>;

		interrupts = <GIC_SPI 75 0>;

		connectors = <&hdmi>;

drivers/gpu/drm/msm/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -54,3 +54,11 @@ config DRM_MSM_DSI_20NM_PHY 
	default y

	help

	  Choose this option if the 20nm DSI PHY is used on the platform.



config DRM_MSM_DSI_28NM_8960_PHY

	bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"

	depends on DRM_MSM_DSI

	default y

	help

	  Choose this option if the 28nm DSI PHY 8960 variant is used on the

	  platform.

drivers/gpu/drm/msm/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o 
msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o



msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \

			mdp/mdp4/mdp4_dsi_encoder.o \

			dsi/dsi_cfg.o \

			dsi/dsi_host.o \

			dsi/dsi_manager.o \
@@ -62,10 +63,12 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ 


msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o

msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o

msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o



ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)

msm-y += dsi/pll/dsi_pll.o

msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o

msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o

endif



obj-$(CONFIG_DRM_MSM)	+= msm.o

drivers/gpu/drm/msm/adreno/adreno_device.c

+0 −52
Original line number Diff line number Diff line
@@ -19,10 +19,6 @@ 


#include "adreno_gpu.h"



#if defined(DOWNSTREAM_CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)

#  include <mach/kgsl.h>

#endif



#define ANY_ID 0xff



bool hang_debug = false;
@@ -168,7 +164,6 @@ static void set_gpu_pdev(struct drm_device *dev, 
static int adreno_bind(struct device *dev, struct device *master, void *data)

{

	static struct adreno_platform_config config = {};

#ifdef CONFIG_OF

	struct device_node *child, *node = dev->of_node;

	u32 val;

	int ret;
@@ -205,53 +200,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) 
		return -ENXIO;

	}



#else

	struct kgsl_device_platform_data *pdata = dev->platform_data;

	uint32_t version = socinfo_get_version();

	if (cpu_is_apq8064ab()) {

		config.fast_rate = 450000000;

		config.slow_rate = 27000000;

		config.bus_freq  = 4;

		config.rev = ADRENO_REV(3, 2, 1, 0);

	} else if (cpu_is_apq8064()) {

		config.fast_rate = 400000000;

		config.slow_rate = 27000000;

		config.bus_freq  = 4;



		if (SOCINFO_VERSION_MAJOR(version) == 2)

			config.rev = ADRENO_REV(3, 2, 0, 2);

		else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&

				(SOCINFO_VERSION_MINOR(version) == 1))

			config.rev = ADRENO_REV(3, 2, 0, 1);

		else

			config.rev = ADRENO_REV(3, 2, 0, 0);



	} else if (cpu_is_msm8960ab()) {

		config.fast_rate = 400000000;

		config.slow_rate = 320000000;

		config.bus_freq  = 4;



		if (SOCINFO_VERSION_MINOR(version) == 0)

			config.rev = ADRENO_REV(3, 2, 1, 0);

		else

			config.rev = ADRENO_REV(3, 2, 1, 1);



	} else if (cpu_is_msm8930()) {

		config.fast_rate = 400000000;

		config.slow_rate = 27000000;

		config.bus_freq  = 3;



		if ((SOCINFO_VERSION_MAJOR(version) == 1) &&

			(SOCINFO_VERSION_MINOR(version) == 2))

			config.rev = ADRENO_REV(3, 0, 5, 2);

		else

			config.rev = ADRENO_REV(3, 0, 5, 0);



	}

#  ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING

	config.bus_scale_table = pdata->bus_scale_table;

#  endif

#endif

	dev->platform_data = &config;

	set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));

	return 0;