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Commit 4510fb98 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: make vm_block_size a module parameter 



Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1c44132

drivers/gpu/drm/radeon/cik.c

+1 −1
Original line number Diff line number Diff line
@@ -5446,7 +5446,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) 
	       (u32)(rdev->dummy_page.addr >> 12));

	WREG32(VM_CONTEXT1_CNTL2, 4);

	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

				PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |

				PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |

				RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

drivers/gpu/drm/radeon/ni.c

+1 −1
Original line number Diff line number Diff line
@@ -1268,7 +1268,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev) 
	       (u32)(rdev->dummy_page.addr >> 12));

	WREG32(VM_CONTEXT1_CNTL2, 4);

	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

				PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |

				PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |

				RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

				RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |

				DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |

drivers/gpu/drm/radeon/radeon.h

+2 −6
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ extern int radeon_aspm; 
extern int radeon_runtime_pm;

extern int radeon_hard_reset;

extern int radeon_vm_size;

extern int radeon_vm_block_size;



/*

 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -838,13 +839,8 @@ struct radeon_mec { 
/* maximum number of VMIDs */

#define RADEON_NUM_VM	16



/* defines number of bits in page table versus page directory,

 * a page is 4KB so we have 12 bits offset, 9 bits in the page

 * table and the remaining 19 bits are in the page directory */

#define RADEON_VM_BLOCK_SIZE   9



/* number of entries in page table */

#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)

#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)



/* PTBs (Page Table Blocks) need to be aligned to 32K */

#define RADEON_VM_PTB_ALIGN_SIZE   32768

drivers/gpu/drm/radeon/radeon_device.c

+16 −0
Original line number Diff line number Diff line
@@ -1073,6 +1073,22 @@ static void radeon_check_arguments(struct radeon_device *rdev) 
			 radeon_vm_size);

		radeon_vm_size = 4096;

	}



	/* defines number of bits in page table versus page directory,

	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the

	 * page table and the remaining bits are in the page directory */

	if (radeon_vm_block_size < 9) {

		dev_warn(rdev->dev, "VM page table size (%d) to small\n",

			 radeon_vm_block_size);

		radeon_vm_block_size = 9;

	}



	if (radeon_vm_block_size > 24 ||

	    radeon_vm_size < (1ull << radeon_vm_block_size)) {

		dev_warn(rdev->dev, "VM page table size (%d) to large\n",

			 radeon_vm_block_size);

		radeon_vm_block_size = 9;

	}

}



/**

drivers/gpu/drm/radeon/radeon_drv.c

+4 −0
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ int radeon_aspm = -1; 
int radeon_runtime_pm = -1;

int radeon_hard_reset = 0;

int radeon_vm_size = 4096;

int radeon_vm_block_size = 9;



MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");

module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -243,6 +244,9 @@ module_param_named(hard_reset, radeon_hard_reset, int, 0444); 
MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)");

module_param_named(vm_size, radeon_vm_size, int, 0444);



MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");

module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);



static struct pci_device_id pciidlist[] = {

	radeon_PCI_IDS

};