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Commit 442e295c authored by Vicky Wallace's avatar Vicky Wallace
Browse files

clk: qcom: Add GPU CC and GFX clock driver support for SDM845 v2 



Add node clock  support for the GFX and GMU V2 frequency plan.

CRs-Fixed: 2088018
Change-Id: I166a840941e04b1e036cd9228fafa86b46b9508d
Signed-off-by: default avatarVicky Wallace <vwallace@codeaurora.org>
parent 1996ec83

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+3 −1
Original line number Diff line number Diff line
@@ -4,7 +4,9 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding 
Required properties :

- compatible : shall contain only one of the following:

		"qcom,gpucc-sdm845",

		"qcom,gfxcc-sdm845"

		"qcom,gpucc-sdm845-v2",

		"qcom,gfxcc-sdm845",

		"qcom,gfxcc-sdm845-v2"



- reg : shall contain base register offset and size.

- #clock-cells : shall contain 1.

drivers/clk/qcom/gpucc-sdm845.c

+117 −0
Original line number Diff line number Diff line
@@ -142,6 +142,11 @@ static const struct pll_config gpu_cc_pll0_config = { 
	.frac = 0x2aaa,

};



static const struct pll_config gpu_cc_pll1_config = {

	.l = 0x1a,

	.frac = 0xaaaa,

};



static struct clk_alpha_pll gpu_cc_pll0 = {

	.offset = 0x0,

	.vco_table = fabia_vco,
@@ -185,6 +190,26 @@ static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = { 
	},

};



static struct clk_alpha_pll gpu_cc_pll1 = {

	.offset = 0x100,

	.vco_table = fabia_vco,

	.num_vco = ARRAY_SIZE(fabia_vco),

	.type = FABIA_PLL,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_pll1",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_fabia_pll_ops,

			VDD_MX_FMAX_MAP4(

				MIN, 615000000,

				LOW, 1066000000,

				LOW_L1, 1600000000,

				NOMINAL, 2000000000),

		},

	},

};



static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
@@ -192,6 +217,13 @@ static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sdm845_v2[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),

	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),

	{ }

};



static struct clk_rcg2 gpu_cc_gmu_clk_src = {

	.cmd_rcgr = 0x1120,

	.mnd_width = 0,
@@ -235,6 +267,18 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { 
	{ }

};



static const struct freq_tbl  ftbl_gpu_cc_gx_gfx3d_clk_src_sdm845_v2[] = {

	F(180000000, P_CRC_DIV,  1, 0, 0),

	F(257000000, P_CRC_DIV,  1, 0, 0),

	F(342000000, P_CRC_DIV,  1, 0, 0),

	F(414000000, P_CRC_DIV,  1, 0, 0),

	F(520000000, P_CRC_DIV,  1, 0, 0),

	F(596000000, P_CRC_DIV,  1, 0, 0),

	F(670000000, P_CRC_DIV,  1, 0, 0),

	F(710000000, P_CRC_DIV,  1, 0, 0),

	{ }

};



static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {

	.cmd_rcgr = 0x101c,

	.mnd_width = 0,
@@ -517,6 +561,7 @@ static struct clk_regmap *gpu_cc_gfx_sdm845_clocks[] = { 
	[GPU_CC_PLL0_OUT_EVEN] = &gpu_cc_pll0_out_even.clkr,

	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,

	[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,

	[GPU_CC_PLL1] = NULL,

};



static const struct qcom_reset_map gpu_cc_sdm845_resets[] = {
@@ -553,16 +598,76 @@ static const struct qcom_cc_desc gpu_cc_gfx_sdm845_desc = { 


static const struct of_device_id gpu_cc_sdm845_match_table[] = {

	{ .compatible = "qcom,gpucc-sdm845" },

	{ .compatible = "qcom,gpucc-sdm845-v2" },

	{ }

};

MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);



static const struct of_device_id gpu_cc_gfx_sdm845_match_table[] = {

	{ .compatible = "qcom,gfxcc-sdm845" },

	{ .compatible = "qcom,gfxcc-sdm845-v2" },

	{},

};

MODULE_DEVICE_TABLE(of, gpu_cc_gfx_sdm845_match_table);



static void gpu_cc_sdm845_fixup_sdm845v2(struct regmap *regmap)

{

	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);

	gpu_cc_sdm845_clocks[GPU_CC_PLL1] = &gpu_cc_pll1.clkr;

	gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sdm845_v2;

	gpu_cc_gmu_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW] = 500000000;

}



static void gpu_cc_gfx_sdm845_fixup_sdm845v2(void)

{

	gpu_cc_gx_gfx3d_clk_src.freq_tbl =

				ftbl_gpu_cc_gx_gfx3d_clk_src_sdm845_v2;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_MIN] = 180000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_LOWER] =

				257000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_LOW] = 342000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_LOW_L1] =

				414000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_NOMINAL] =

				520000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_NOMINAL_L1] =

				596000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_HIGH] = 675000000;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_GX_HIGH_L1] =

				710000000;

}



static int gpu_cc_gfx_sdm845_fixup(struct platform_device *pdev)

{

	const char *compat = NULL;

	int compatlen = 0;



	compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);

	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,gfxcc-sdm845-v2"))

		gpu_cc_gfx_sdm845_fixup_sdm845v2();



	return 0;

}



static int gpu_cc_sdm845_fixup(struct platform_device *pdev,

					struct regmap *regmap)

{

	const char *compat = NULL;

	int compatlen = 0;



	compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);

	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,gpucc-sdm845-v2"))

		gpu_cc_sdm845_fixup_sdm845v2(regmap);



	return 0;

}



static int gpu_cc_gfx_sdm845_probe(struct platform_device *pdev)

{

	struct regmap *regmap;
@@ -616,6 +721,12 @@ static int gpu_cc_gfx_sdm845_probe(struct platform_device *pdev) 
	/* Avoid turning on the rail during clock registration */

	vdd_gfx.skip_handoff = true;



	ret = gpu_cc_gfx_sdm845_fixup(pdev);

	if (ret) {

		dev_err(&pdev->dev, "Failed to do GFX clock fixup\n");

		return ret;

	}



	clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_gfx_sdm845_desc, regmap);
@@ -668,6 +779,12 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_cx.regulator[0]);

	}



	ret = gpu_cc_sdm845_fixup(pdev, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to do GPU CC clock fixup\n");

		return ret;

	}



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");