Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 (4406c56d) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/ABI/testing/sysfs-bus-pci

+10 −0

Original line number	Original line	Diff line number	Diff line
	@@ -84,6 +84,16 @@ Description:
	from this part of the device tree.		from this part of the device tree.
	Depends on CONFIG_HOTPLUG.		Depends on CONFIG_HOTPLUG.

			What: /sys/bus/pci/devices/.../reset
			Date: July 2009
			Contact: Michael S. Tsirkin <mst@redhat.com>
			Description:
			Some devices allow an individual function to be reset
			without affecting other functions in the same device.
			For devices that have this support, a file named reset
			will be present in sysfs. Writing 1 to this file
			will perform reset.

	What: /sys/bus/pci/devices/.../vpd		What: /sys/bus/pci/devices/.../vpd
	Date: February 2008		Date: February 2008
	Contact: Ben Hutchings <bhutchings@solarflare.com>		Contact: Ben Hutchings <bhutchings@solarflare.com>

Documentation/PCI/pci-error-recovery.txt

+77 −42

Original line number	Original line	Diff line number	Diff line
	@@ -4,15 +4,17 @@
	February 2, 2006		February 2, 2006

	Current document maintainer:		Current document maintainer:
	Linas Vepstas <linas@austin.ibm.com>		Linas Vepstas <linasvepstas@gmail.com>
			updated by Richard Lary <rlary@us.ibm.com>
			and Mike Mason <mmlnx@us.ibm.com> on 27-Jul-2009


	Many PCI bus controllers are able to detect a variety of hardware		Many PCI bus controllers are able to detect a variety of hardware
	PCI errors on the bus, such as parity errors on the data and address		PCI errors on the bus, such as parity errors on the data and address
	busses, as well as SERR and PERR errors. Some of the more advanced		busses, as well as SERR and PERR errors. Some of the more advanced
	chipsets are able to deal with these errors; these include PCI-E chipsets,		chipsets are able to deal with these errors; these include PCI-E chipsets,
	and the PCI-host bridges found on IBM Power4 and Power5-based pSeries		and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
	boxes. A typical action taken is to disconnect the affected device,		pSeries boxes. A typical action taken is to disconnect the affected device,
	halting all I/O to it. The goal of a disconnection is to avoid system		halting all I/O to it. The goal of a disconnection is to avoid system
	corruption; for example, to halt system memory corruption due to DMA's		corruption; for example, to halt system memory corruption due to DMA's
	to "wild" addresses. Typically, a reconnection mechanism is also		to "wild" addresses. Typically, a reconnection mechanism is also
	@@ -37,10 +39,11 @@ is forced by the need to handle multi-function devices, that is,
	devices that have multiple device drivers associated with them.		devices that have multiple device drivers associated with them.
	In the first stage, each driver is allowed to indicate what type		In the first stage, each driver is allowed to indicate what type
	of reset it desires, the choices being a simple re-enabling of I/O		of reset it desires, the choices being a simple re-enabling of I/O
	or requesting a hard reset (a full electrical #RST of the PCI card).		or requesting a slot reset.
	If any driver requests a full reset, that is what will be done.

	After a full reset and/or a re-enabling of I/O, all drivers are		If any driver requests a slot reset, that is what will be done.

			After a reset and/or a re-enabling of I/O, all drivers are
	again notified, so that they may then perform any device setup/config		again notified, so that they may then perform any device setup/config
	that may be required. After these have all completed, a final		that may be required. After these have all completed, a final
	"resume normal operations" event is sent out.		"resume normal operations" event is sent out.
	@@ -101,7 +104,7 @@ if it implements any, it must implement error_detected(). If a callback
	is not implemented, the corresponding feature is considered unsupported.		is not implemented, the corresponding feature is considered unsupported.
	For example, if mmio_enabled() and resume() aren't there, then it		For example, if mmio_enabled() and resume() aren't there, then it
	is assumed that the driver is not doing any direct recovery and requires		is assumed that the driver is not doing any direct recovery and requires
	a reset. If link_reset() is not implemented, the card is assumed as		a slot reset. If link_reset() is not implemented, the card is assumed to
	not care about link resets. Typically a driver will want to know about		not care about link resets. Typically a driver will want to know about
	a slot_reset().		a slot_reset().

	@@ -111,7 +114,7 @@ sequence described below.

	STEP 0: Error Event		STEP 0: Error Event
	-------------------		-------------------
	PCI bus error is detect by the PCI hardware. On powerpc, the slot		A PCI bus error is detected by the PCI hardware. On powerpc, the slot
	is isolated, in that all I/O is blocked: all reads return 0xffffffff,		is isolated, in that all I/O is blocked: all reads return 0xffffffff,
	all writes are ignored.		all writes are ignored.

	@@ -139,7 +142,7 @@ The driver must return one of the following result codes:
	a chance to extract some diagnostic information (see		a chance to extract some diagnostic information (see
	mmio_enable, below).		mmio_enable, below).
	- PCI_ERS_RESULT_NEED_RESET:		- PCI_ERS_RESULT_NEED_RESET:
	Driver returns this if it can't recover without a hard		Driver returns this if it can't recover without a
	slot reset.		slot reset.
	- PCI_ERS_RESULT_DISCONNECT:		- PCI_ERS_RESULT_DISCONNECT:
	Driver returns this if it doesn't want to recover at all.		Driver returns this if it doesn't want to recover at all.
	@@ -169,11 +172,11 @@ is STEP 6 (Permanent Failure).

	>>> The current powerpc implementation doesn't much care if the device		>>> The current powerpc implementation doesn't much care if the device
	>>> attempts I/O at this point, or not. I/O's will fail, returning		>>> attempts I/O at this point, or not. I/O's will fail, returning
	>>> a value of 0xff on read, and writes will be dropped. If the device		>>> a value of 0xff on read, and writes will be dropped. If more than
	>>> driver attempts more than 10K I/O's to a frozen adapter, it will		>>> EEH_MAX_FAILS I/O's are attempted to a frozen adapter, EEH
	>>> assume that the device driver has gone into an infinite loop, and		>>> assumes that the device driver has gone into an infinite loop
	>>> it will panic the kernel. There doesn't seem to be any other		>>> and prints an error to syslog. A reboot is then required to
	>>> way of stopping a device driver that insists on spinning on I/O.		>>> get the device working again.

	STEP 2: MMIO Enabled		STEP 2: MMIO Enabled
	-------------------		-------------------
	@@ -182,15 +185,14 @@ DMA), and then calls the mmio_enabled() callback on all affected
	device drivers.		device drivers.

	This is the "early recovery" call. IOs are allowed again, but DMA is		This is the "early recovery" call. IOs are allowed again, but DMA is
	not (hrm... to be discussed, I prefer not), with some restrictions. This		not, with some restrictions. This is NOT a callback for the driver to
	is NOT a callback for the driver to start operations again, only to		start operations again, only to peek/poke at the device, extract diagnostic
	peek/poke at the device, extract diagnostic information, if any, and		information, if any, and eventually do things like trigger a device local
	eventually do things like trigger a device local reset or some such,		reset or some such, but not restart operations. This callback is made if
	but not restart operations. This is callback is made if all drivers on		all drivers on a segment agree that they can try to recover and if no automatic
	a segment agree that they can try to recover and if no automatic link reset		link reset was performed by the HW. If the platform can't just re-enable IOs
	was performed by the HW. If the platform can't just re-enable IOs without		without a slot reset or a link reset, it will not call this callback, and
	a slot reset or a link reset, it wont call this callback, and instead		instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
	will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)

	>>> The following is proposed; no platform implements this yet:		>>> The following is proposed; no platform implements this yet:
	>>> Proposal: All I/O's should be done _synchronously_ from within		>>> Proposal: All I/O's should be done _synchronously_ from within
	@@ -228,9 +230,6 @@ proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
	If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform		If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
	proceeds to STEP 4 (Slot Reset)		proceeds to STEP 4 (Slot Reset)

	>>> The current powerpc implementation does not implement this callback.


	STEP 3: Link Reset		STEP 3: Link Reset
	------------------		------------------
	The platform resets the link, and then calls the link_reset() callback		The platform resets the link, and then calls the link_reset() callback
	@@ -253,16 +252,33 @@ The platform then proceeds to either STEP 4 (Slot Reset) or STEP 5

	>>> The current powerpc implementation does not implement this callback.		>>> The current powerpc implementation does not implement this callback.


	STEP 4: Slot Reset		STEP 4: Slot Reset
	------------------		------------------
	The platform performs a soft or hard reset of the device, and then
	calls the slot_reset() callback.

	A soft reset consists of asserting the adapter #RST line and then		In response to a return value of PCI_ERS_RESULT_NEED_RESET, the
			the platform will peform a slot reset on the requesting PCI device(s).
			The actual steps taken by a platform to perform a slot reset
			will be platform-dependent. Upon completion of slot reset, the
			platform will call the device slot_reset() callback.

			Powerpc platforms implement two levels of slot reset:
			soft reset(default) and fundamental(optional) reset.

			Powerpc soft reset consists of asserting the adapter #RST line and then
	restoring the PCI BAR's and PCI configuration header to a state		restoring the PCI BAR's and PCI configuration header to a state
	that is equivalent to what it would be after a fresh system		that is equivalent to what it would be after a fresh system
	power-on followed by power-on BIOS/system firmware initialization.		power-on followed by power-on BIOS/system firmware initialization.
			Soft reset is also known as hot-reset.

			Powerpc fundamental reset is supported by PCI Express cards only
			and results in device's state machines, hardware logic, port states and
			configuration registers to initialize to their default conditions.

			For most PCI devices, a soft reset will be sufficient for recovery.
			Optional fundamental reset is provided to support a limited number
			of PCI Express PCI devices for which a soft reset is not sufficient
			for recovery.

	If the platform supports PCI hotplug, then the reset might be		If the platform supports PCI hotplug, then the reset might be
	performed by toggling the slot electrical power off/on.		performed by toggling the slot electrical power off/on.

	@@ -274,10 +290,12 @@ may result in hung devices, kernel panics, or silent data corruption.

	This call gives drivers the chance to re-initialize the hardware		This call gives drivers the chance to re-initialize the hardware
	(re-download firmware, etc.). At this point, the driver may assume		(re-download firmware, etc.). At this point, the driver may assume
	that he card is in a fresh state and is fully functional. In		that the card is in a fresh state and is fully functional. The slot
	particular, interrupt generation should work normally.		is unfrozen and the driver has full access to PCI config space,
			memory mapped I/O space and DMA. Interrupts (Legacy, MSI, or MSI-X)
			will also be available.

	Drivers should not yet restart normal I/O processing operations		Drivers should not restart normal I/O processing operations
	at this point. If all device drivers report success on this		at this point. If all device drivers report success on this
	callback, the platform will call resume() to complete the sequence,		callback, the platform will call resume() to complete the sequence,
	and let the driver restart normal I/O processing.		and let the driver restart normal I/O processing.
	@@ -302,11 +320,21 @@ driver performs device init only from PCI function 0:
	- PCI_ERS_RESULT_DISCONNECT		- PCI_ERS_RESULT_DISCONNECT
	Same as above.		Same as above.

			Drivers for PCI Express cards that require a fundamental reset must
			set the needs_freset bit in the pci_dev structure in their probe function.
			For example, the QLogic qla2xxx driver sets the needs_freset bit for certain
			PCI card types:

			+ /* Set EEH reset type to fundamental if required by hba */
			+ if (IS_QLA24XX(ha) \|\| IS_QLA25XX(ha) \|\| IS_QLA81XX(ha))
			+ pdev->needs_freset = 1;
			+

	Platform proceeds either to STEP 5 (Resume Operations) or STEP 6 (Permanent		Platform proceeds either to STEP 5 (Resume Operations) or STEP 6 (Permanent
	Failure).		Failure).

	>>> The current powerpc implementation does not currently try a		>>> The current powerpc implementation does not try a power-cycle
	>>> power-cycle reset if the driver returned PCI_ERS_RESULT_DISCONNECT.		>>> reset if the driver returned PCI_ERS_RESULT_DISCONNECT.
	>>> However, it probably should.		>>> However, it probably should.


	@@ -348,7 +376,7 @@ software errors.

	Conclusion; General Remarks		Conclusion; General Remarks
	---------------------------		---------------------------
	The way those callbacks are called is platform policy. A platform with		The way the callbacks are called is platform policy. A platform with
	no slot reset capability may want to just "ignore" drivers that can't		no slot reset capability may want to just "ignore" drivers that can't
	recover (disconnect them) and try to let other cards on the same segment		recover (disconnect them) and try to let other cards on the same segment
	recover. Keep in mind that in most real life cases, though, there will		recover. Keep in mind that in most real life cases, though, there will
	@@ -361,8 +389,8 @@ That is, the recovery API only requires that:

	- There is no guarantee that interrupt delivery can proceed from any		- There is no guarantee that interrupt delivery can proceed from any
	device on the segment starting from the error detection and until the		device on the segment starting from the error detection and until the
	resume callback is sent, at which point interrupts are expected to be		slot_reset callback is called, at which point interrupts are expected
	fully operational.		to be fully operational.

	- There is no guarantee that interrupt delivery is stopped, that is,		- There is no guarantee that interrupt delivery is stopped, that is,
	a driver that gets an interrupt after detecting an error, or that detects		a driver that gets an interrupt after detecting an error, or that detects
	@@ -381,16 +409,23 @@ anyway :)
	>>> Implementation details for the powerpc platform are discussed in		>>> Implementation details for the powerpc platform are discussed in
	>>> the file Documentation/powerpc/eeh-pci-error-recovery.txt		>>> the file Documentation/powerpc/eeh-pci-error-recovery.txt

	>>> As of this writing, there are six device drivers with patches		>>> As of this writing, there is a growing list of device drivers with
	>>> implementing error recovery. Not all of these patches are in		>>> patches implementing error recovery. Not all of these patches are in
	>>> mainline yet. These may be used as "examples":		>>> mainline yet. These may be used as "examples":
	>>>		>>>
	>>> drivers/scsi/ipr.c		>>> drivers/scsi/ipr
	>>> drivers/scsi/sym53cxx_2		>>> drivers/scsi/sym53c8xx_2
			>>> drivers/scsi/qla2xxx
			>>> drivers/scsi/lpfc
			>>> drivers/next/bnx2.c
	>>> drivers/next/e100.c		>>> drivers/next/e100.c
	>>> drivers/net/e1000		>>> drivers/net/e1000
			>>> drivers/net/e1000e
	>>> drivers/net/ixgb		>>> drivers/net/ixgb
			>>> drivers/net/ixgbe
			>>> drivers/net/cxgb3
	>>> drivers/net/s2io.c		>>> drivers/net/s2io.c
			>>> drivers/net/qlge

	The End		The End
	-------		-------

Documentation/vgaarbiter.txt

0 → 100644

+194 −0

Original line number	Original line	Diff line number	Diff line

			VGA Arbiter
			===========

			Graphic devices are accessed through ranges in I/O or memory space. While most
			modern devices allow relocation of such ranges, some "Legacy" VGA devices
			implemented on PCI will typically have the same "hard-decoded" addresses as
			they did on ISA. For more details see "PCI Bus Binding to IEEE Std 1275-1994
			Standard for Boot (Initialization Configuration) Firmware Revision 2.1"
			Section 7, Legacy Devices.

			The Resource Access Control (RAC) module inside the X server [0] existed for
			the legacy VGA arbitration task (besides other bus management tasks) when more
			than one legacy device co-exists on the same machine. But the problem happens
			when these devices are trying to be accessed by different userspace clients
			(e.g. two server in parallel). Their address assignments conflict. Moreover,
			ideally, being an userspace application, it is not the role of the the X
			server to control bus resources. Therefore an arbitration scheme outside of
			the X server is needed to control the sharing of these resources. This
			document introduces the operation of the VGA arbiter implemented for Linux
			kernel.

			----------------------------------------------------------------------------

			I. Details and Theory of Operation
			I.1 vgaarb
			I.2 libpciaccess
			I.3 xf86VGAArbiter (X server implementation)
			II. Credits
			III.References


			I. Details and Theory of Operation
			==================================

			I.1 vgaarb
			----------

			The vgaarb is a module of the Linux Kernel. When it is initially loaded, it
			scans all PCI devices and adds the VGA ones inside the arbitration. The
			arbiter then enables/disables the decoding on different devices of the VGA
			legacy instructions. Device which do not want/need to use the arbiter may
			explicitly tell it by calling vga_set_legacy_decoding().

			The kernel exports a char device interface (/dev/vga_arbiter) to the clients,
			which has the following semantics:

			open : open user instance of the arbiter. By default, it's attached to
			the default VGA device of the system.

			close : close user instance. Release locks made by the user

			read : return a string indicating the status of the target like:

			"<card_ID>,decodes=<io_state>,owns=<io_state>,locks=<io_state> (ic,mc)"

			An IO state string is of the form {io,mem,io+mem,none}, mc and
			ic are respectively mem and io lock counts (for debugging/
			diagnostic only). "decodes" indicate what the card currently
			decodes, "owns" indicates what is currently enabled on it, and
			"locks" indicates what is locked by this card. If the card is
			unplugged, we get "invalid" then for card_ID and an -ENODEV
			error is returned for any command until a new card is targeted.


			write : write a command to the arbiter. List of commands:

			target <card_ID> : switch target to card <card_ID> (see below)
			lock <io_state> : acquires locks on target ("none" is an invalid io_state)
			trylock <io_state> : non-blocking acquire locks on target (returns EBUSY if
			unsuccessful)
			unlock <io_state> : release locks on target
			unlock all : release all locks on target held by this user (not
			implemented yet)
			decodes <io_state> : set the legacy decoding attributes for the card

			poll : event if something changes on any card (not just the
			target)

			card_ID is of the form "PCI:domain:bus:dev.fn". It can be set to "default"
			to go back to the system default card (TODO: not implemented yet). Currently,
			only PCI is supported as a prefix, but the userland API may support other bus
			types in the future, even if the current kernel implementation doesn't.

			Note about locks:

			The driver keeps track of which user has which locks on which card. It
			supports stacking, like the kernel one. This complexifies the implementation
			a bit, but makes the arbiter more tolerant to user space problems and able
			to properly cleanup in all cases when a process dies.
			Currently, a max of 16 cards can have locks simultaneously issued from
			user space for a given user (file descriptor instance) of the arbiter.

			In the case of devices hot-{un,}plugged, there is a hook - pci_notify() - to
			notify them being added/removed in the system and automatically added/removed
			in the arbiter.

			There's also a in-kernel API of the arbiter in the case of DRM, vgacon and
			others which may use the arbiter.


			I.2 libpciaccess
			----------------

			To use the vga arbiter char device it was implemented an API inside the
			libpciaccess library. One fieldd was added to struct pci_device (each device
			on the system):

			/* the type of resource decoded by the device */
			int vgaarb_rsrc;

			Besides it, in pci_system were added:

			int vgaarb_fd;
			int vga_count;
			struct pci_device *vga_target;
			struct pci_device *vga_default_dev;


			The vga_count is usually need to keep informed how many cards are being
			arbitrated, so for instance if there's only one then it can totally escape the
			scheme.


			These functions below acquire VGA resources for the given card and mark those
			resources as locked. If the resources requested are "normal" (and not legacy)
			resources, the arbiter will first check whether the card is doing legacy
			decoding for that type of resource. If yes, the lock is "converted" into a
			legacy resource lock. The arbiter will first look for all VGA cards that
			might conflict and disable their IOs and/or Memory access, including VGA
			forwarding on P2P bridges if necessary, so that the requested resources can
			be used. Then, the card is marked as locking these resources and the IO and/or
			Memory access is enabled on the card (including VGA forwarding on parent
			P2P bridges if any). In the case of vga_arb_lock(), the function will block
			if some conflicting card is already locking one of the required resources (or
			any resource on a different bus segment, since P2P bridges don't differentiate
			VGA memory and IO afaik). If the card already owns the resources, the function
			succeeds. vga_arb_trylock() will return (-EBUSY) instead of blocking. Nested
			calls are supported (a per-resource counter is maintained).


			Set the target device of this client.
			int pci_device_vgaarb_set_target (struct pci_device *dev);


			For instance, in x86 if two devices on the same bus want to lock different
			resources, both will succeed (lock). If devices are in different buses and
			trying to lock different resources, only the first who tried succeeds.
			int pci_device_vgaarb_lock (void);
			int pci_device_vgaarb_trylock (void);

			Unlock resources of device.
			int pci_device_vgaarb_unlock (void);

			Indicates to the arbiter if the card decodes legacy VGA IOs, legacy VGA
			Memory, both, or none. All cards default to both, the card driver (fbdev for
			example) should tell the arbiter if it has disabled legacy decoding, so the
			card can be left out of the arbitration process (and can be safe to take
			interrupts at any time.
			int pci_device_vgaarb_decodes (int new_vgaarb_rsrc);

			Connects to the arbiter device, allocates the struct
			int pci_device_vgaarb_init (void);

			Close the connection
			void pci_device_vgaarb_fini (void);


			I.3 xf86VGAArbiter (X server implementation)
			--------------------------------------------

			(TODO)

			X server basically wraps all the functions that touch VGA registers somehow.


			II. Credits
			===========

			Benjamin Herrenschmidt (IBM?) started this work when he discussed such design
			with the Xorg community in 2005 [1, 2]. In the end of 2007, Paulo Zanoni and
			Tiago Vignatti (both of C3SL/Federal University of Paraná) proceeded his work
			enhancing the kernel code to adapt as a kernel module and also did the
			implementation of the user space side [3]. Now (2009) Tiago Vignatti and Dave
			Airlie finally put this work in shape and queued to Jesse Barnes' PCI tree.


			III. References
			==============

			[0] http://cgit.freedesktop.org/xorg/xserver/commit/?id=4b42448a2388d40f257774fbffdccaea87bd0347
			[1] http://lists.freedesktop.org/archives/xorg/2005-March/006663.html
			[2] http://lists.freedesktop.org/archives/xorg/2005-March/006745.html
			[3] http://lists.freedesktop.org/archives/xorg/2007-October/029507.html

arch/alpha/include/asm/pci.h

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -52,7 +52,6 @@ struct pci_controller {
	bus numbers. */		bus numbers. */

	#define pcibios_assign_all_busses() 1		#define pcibios_assign_all_busses() 1
	#define pcibios_scan_all_fns(a, b) 0

	#define PCIBIOS_MIN_IO alpha_mv.min_io_address		#define PCIBIOS_MIN_IO alpha_mv.min_io_address
	#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address		#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address

arch/arm/include/asm/pci.h

+0 −2

Original line number	Original line	Diff line number	Diff line
	@@ -6,8 +6,6 @@

	#include <mach/hardware.h> /* for PCIBIOS_MIN_* */		#include <mach/hardware.h> /* for PCIBIOS_MIN_* */

	#define pcibios_scan_all_fns(a, b) 0

	#ifdef CONFIG_PCI_HOST_ITE8152		#ifdef CONFIG_PCI_HOST_ITE8152
	/* ITE bridge requires setting latency timer to avoid early bus access		/* ITE bridge requires setting latency timer to avoid early bus access
	termination by PIC bus mater devices		termination by PIC bus mater devices