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Commit 43db9370 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: clk-cpu-osm: Add an additional voter clock for L3 



Add a new l3_misc_vote_clk clock for clients to use to
cast rate and enable votes on the L3 cluster clock.

Change-Id: I1fec757426e2c0666c8333f9b33b8fc1be0833dc
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent cc8c86a2

drivers/clk/qcom/clk-cpu-osm.c

+4 −0
Original line number Diff line number Diff line
@@ -268,6 +268,7 @@ static struct clk_osm l3_clk = { 


static DEFINE_CLK_VOTER(l3_cluster0_vote_clk, l3_clk, 0);

static DEFINE_CLK_VOTER(l3_cluster1_vote_clk, l3_clk, 0);

static DEFINE_CLK_VOTER(l3_misc_vote_clk, l3_clk, 0);



static struct clk_osm pwrcl_clk = {

	.cluster_num = 1,
@@ -380,6 +381,7 @@ static struct clk_hw *osm_qcom_clk_hws[] = { 
	[L3_CLK] = &l3_clk.hw,

	[L3_CLUSTER0_VOTE_CLK] = &l3_cluster0_vote_clk.hw,

	[L3_CLUSTER1_VOTE_CLK] = &l3_cluster1_vote_clk.hw,

	[L3_MISC_VOTE_CLK] = &l3_misc_vote_clk.hw,

	[PWRCL_CLK] = &pwrcl_clk.hw,

	[CPU0_PWRCL_CLK] = &cpu0_pwrcl_clk.hw,

	[CPU1_PWRCL_CLK] = &cpu1_pwrcl_clk.hw,
@@ -979,6 +981,8 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) 
			"clk: Failed to enable cluster0 clock for L3\n");

	WARN(clk_prepare_enable(l3_cluster1_vote_clk.hw.clk),

			"clk: Failed to enable cluster1 clock for L3\n");

	WARN(clk_prepare_enable(l3_misc_vote_clk.hw.clk),

			"clk: Failed to enable misc clock for L3\n");



	populate_opp_table(pdev);

include/dt-bindings/clock/qcom,cpucc-sdm845.h

+1 −0
Original line number Diff line number Diff line
@@ -27,5 +27,6 @@ 
#define CPU5_PERFCL_CLK						10

#define CPU6_PERFCL_CLK						11

#define CPU7_PERFCL_CLK						12

#define L3_MISC_VOTE_CLK					13



#endif