[IA64-SGI] cleanup shubio.h (43cc6725) · Commits · e / devices / android_kernel_fairphone_FP3

include/asm-ia64/sn/shubio.h

+1499 −1617

Original line number	Diff line number	Diff line
		@@ -3,7 +3,7 @@
		* License. See the file "COPYING" in the main directory of this archive
		* for more details.
		*
		* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
		* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
		*/

		#ifndef _ASM_IA64_SN_SHUBIO_H
		@@ -65,7 +65,6 @@
		#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
		#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */


		#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
		#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */

		@@ -216,7 +215,6 @@
		#define IIO_IPCR 0x00430000 /* IO Performance Control */
		#define IIO_IPPR 0x00430008 /* IO Performance Profiling */


		/************************************************************************
		* *
		* Description: This register echoes some information from the *
		@@ -239,7 +237,6 @@ typedef union ii_wid_u {
		} ii_wid_fld_s;
		} ii_wid_u_t;


		/************************************************************************
		* *
		* The fields in this register are set upon detection of an error *
		@@ -264,7 +261,6 @@ typedef union ii_wstat_u {
		} ii_wstat_fld_s;
		} ii_wstat_u_t;


		/************************************************************************
		* *
		* Description: This is a read-write enabled register. It controls *
		@@ -286,7 +282,6 @@ typedef union ii_wcr_u {
		} ii_wcr_fld_s;
		} ii_wcr_u_t;


		/************************************************************************
		* *
		* Description: This register's value is a bit vector that guards *
		@@ -321,9 +316,6 @@ typedef union ii_ilapr_u {
		} ii_ilapr_fld_s;
		} ii_ilapr_u_t;




		/************************************************************************
		* *
		* Description: A write to this register of the 64-bit value *
		@@ -344,8 +336,6 @@ typedef union ii_ilapo_u {
		} ii_ilapo_fld_s;
		} ii_ilapo_u_t;



		/************************************************************************
		* *
		* This register qualifies all the PIO and Graphics writes launched *
		@@ -363,7 +353,6 @@ typedef union ii_iowa_u {
		} ii_iowa_fld_s;
		} ii_iowa_u_t;


		/************************************************************************
		* *
		* Description: This register qualifies all the requests launched *
		@@ -383,8 +372,6 @@ typedef union ii_iiwa_u {
		} ii_iiwa_fld_s;
		} ii_iiwa_u_t;



		/************************************************************************
		* *
		* Description: This register qualifies all the operations launched *
		@@ -418,7 +405,6 @@ typedef union ii_iidem_u {
		} ii_iidem_fld_s;
		} ii_iidem_u_t;


		/************************************************************************
		* *
		* This register contains the various programmable fields necessary *
		@@ -447,7 +433,6 @@ typedef union ii_ilcsr_u {
		} ii_ilcsr_fld_s;
		} ii_ilcsr_u_t;


		/************************************************************************
		* *
		* This is simply a status registers that monitors the LLP error *
		@@ -464,7 +449,6 @@ typedef union ii_illr_u {
		} ii_illr_fld_s;
		} ii_illr_u_t;


		/************************************************************************
		* *
		* Description: All II-detected non-BTE error interrupts are *
		@@ -496,8 +480,6 @@ typedef union ii_iidsr_u {
		} ii_iidsr_fld_s;
		} ii_iidsr_u_t;



		/************************************************************************
		* *
		* There are two instances of this register. This register is used *
		@@ -520,7 +502,6 @@ typedef union ii_igfx0_u {
		} ii_igfx0_fld_s;
		} ii_igfx0_u_t;


		/************************************************************************
		* *
		* There are two instances of this register. This register is used *
		@@ -543,7 +524,6 @@ typedef union ii_igfx1_u {
		} ii_igfx1_fld_s;
		} ii_igfx1_u_t;


		/************************************************************************
		* *
		* There are two instances of this registers. These registers are *
		@@ -558,8 +538,6 @@ typedef union ii_iscr0_u {
		} ii_iscr0_fld_s;
		} ii_iscr0_u_t;



		/************************************************************************
		* *
		* There are two instances of this registers. These registers are *
		@@ -574,7 +552,6 @@ typedef union ii_iscr1_u {
		} ii_iscr1_fld_s;
		} ii_iscr1_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -613,7 +590,6 @@ typedef union ii_itte1_u {
		} ii_itte1_fld_s;
		} ii_itte1_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -652,7 +628,6 @@ typedef union ii_itte2_u {
		} ii_itte2_fld_s;
		} ii_itte2_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -691,7 +666,6 @@ typedef union ii_itte3_u {
		} ii_itte3_fld_s;
		} ii_itte3_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -730,7 +704,6 @@ typedef union ii_itte4_u {
		} ii_itte4_fld_s;
		} ii_itte4_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -769,7 +742,6 @@ typedef union ii_itte5_u {
		} ii_itte5_fld_s;
		} ii_itte5_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -808,7 +780,6 @@ typedef union ii_itte6_u {
		} ii_itte6_fld_s;
		} ii_itte6_u_t;


		/************************************************************************
		* *
		* Description: There are seven instances of translation table entry *
		@@ -847,7 +818,6 @@ typedef union ii_itte7_u {
		} ii_itte7_fld_s;
		} ii_itte7_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -892,7 +862,6 @@ typedef union ii_iprb0_u {
		} ii_iprb0_fld_s;
		} ii_iprb0_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -937,7 +906,6 @@ typedef union ii_iprb8_u {
		} ii_iprb8_fld_s;
		} ii_iprb8_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -982,7 +950,6 @@ typedef union ii_iprb9_u {
		} ii_iprb9_fld_s;
		} ii_iprb9_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -1027,7 +994,6 @@ typedef union ii_iprba_u {
		} ii_iprba_fld_s;
		} ii_iprba_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -1072,7 +1038,6 @@ typedef union ii_iprbb_u {
		} ii_iprbb_fld_s;
		} ii_iprbb_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -1117,7 +1082,6 @@ typedef union ii_iprbc_u {
		} ii_iprbc_fld_s;
		} ii_iprbc_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -1162,7 +1126,6 @@ typedef union ii_iprbd_u {
		} ii_iprbd_fld_s;
		} ii_iprbd_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -1207,7 +1170,6 @@ typedef union ii_iprbe_u {
		} ii_iprbe_fld_s;
		} ii_iprbe_u_t;


		/************************************************************************
		* *
		* Description: There are 9 instances of this register, one per *
		@@ -1252,7 +1214,6 @@ typedef union ii_iprbf_u {
		} ii_iprbe_fld_s;
		} ii_iprbf_u_t;


		/************************************************************************
		* *
		* This register specifies the timeout value to use for monitoring *
		@@ -1278,7 +1239,6 @@ typedef union ii_ixcc_u {
		} ii_ixcc_fld_s;
		} ii_ixcc_u_t;


		/************************************************************************
		* *
		* Description: This register qualifies all the PIO and DMA *
		@@ -1309,8 +1269,6 @@ typedef union ii_imem_u {
		} ii_imem_fld_s;
		} ii_imem_u_t;



		/************************************************************************
		* *
		* Description: This register specifies the timeout value to use for *
		@@ -1346,7 +1304,6 @@ typedef union ii_ixtt_u {
		} ii_ixtt_fld_s;
		} ii_ixtt_u_t;


		/************************************************************************
		* *
		* Writing a 1 to the fields of this register clears the appropriate *
		@@ -1393,7 +1350,6 @@ typedef union ii_ieclr_u {
		} ii_ieclr_fld_s;
		} ii_ieclr_u_t;


		/************************************************************************
		* *
		* This register controls both BTEs. SOFT_RESET is intended for *
		@@ -1413,7 +1369,6 @@ typedef union ii_ibcr_u {
		} ii_ibcr_fld_s;
		} ii_ibcr_u_t;


		/************************************************************************
		* *
		* This register contains the header of a spurious read response *
		@@ -1463,7 +1418,6 @@ typedef union ii_ixsm_u {
		} ii_ixsm_fld_s;
		} ii_ixsm_u_t;


		/************************************************************************
		* *
		* This register contains the sideband bits of a spurious read *
		@@ -1480,7 +1434,6 @@ typedef union ii_ixss_u {
		} ii_ixss_fld_s;
		} ii_ixss_u_t;


		/************************************************************************
		* *
		* This register enables software to access the II LLP's test port. *
		@@ -1508,7 +1461,6 @@ typedef union ii_ilct_u {
		} ii_ilct_fld_s;
		} ii_ilct_u_t;


		/************************************************************************
		* *
		* If the II detects an illegal incoming Duplonet packet (request or *
		@@ -1547,7 +1499,6 @@ typedef union ii_iieph1_u {
		} ii_iieph1_fld_s;
		} ii_iieph1_u_t;


		/************************************************************************
		* *
		* This register holds the Address field from the header flit of an *
		@@ -1570,11 +1521,8 @@ typedef union ii_iieph2_u {
		} ii_iieph2_fld_s;
		} ii_iieph2_u_t;


		/******************************/



		/************************************************************************
		* *
		* This register's value is a bit vector that guards access from SXBs *
		@@ -1590,7 +1538,6 @@ typedef union ii_islapr_u {
		} ii_islapr_fld_s;
		} ii_islapr_u_t;


		/************************************************************************
		* *
		* A write to this register of the 56-bit value "Pup+Bun" will cause *
		@@ -1730,7 +1677,6 @@ typedef union ii_iweim_u {
		} ii_iweim_fld_s;
		} ii_iweim_u_t;


		/************************************************************************
		* *
		* A write to this register causes a particular field in the *
		@@ -1752,7 +1698,6 @@ typedef union ii_ipca_u {
		} ii_ipca_fld_s;
		} ii_ipca_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1763,7 +1708,6 @@ typedef union ii_ipca_u {
		* *
		************************************************************************/


		typedef union ii_iprte0a_u {
		uint64_t ii_iprte0a_regval;
		struct {
		@@ -1774,7 +1718,6 @@ typedef union ii_iprte0a_u {
		} ii_iprte0a_fld_s;
		} ii_iprte0a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1795,7 +1738,6 @@ typedef union ii_iprte1a_u {
		} ii_iprte1a_fld_s;
		} ii_iprte1a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1816,7 +1758,6 @@ typedef union ii_iprte2a_u {
		} ii_iprte2a_fld_s;
		} ii_iprte2a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1837,7 +1778,6 @@ typedef union ii_iprte3a_u {
		} ii_iprte3a_fld_s;
		} ii_iprte3a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1858,7 +1798,6 @@ typedef union ii_iprte4a_u {
		} ii_iprte4a_fld_s;
		} ii_iprte4a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1879,7 +1818,6 @@ typedef union ii_iprte5a_u {
		} ii_iprte5a_fld_s;
		} ii_iprte5a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1900,7 +1838,6 @@ typedef union ii_iprte6a_u {
		} ii_iprte6a_fld_s;
		} ii_iprte6a_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1921,8 +1858,6 @@ typedef union ii_iprte7a_u {
		} ii_iprtea7_fld_s;
		} ii_iprte7a_u_t;



		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1933,7 +1868,6 @@ typedef union ii_iprte7a_u {
		* *
		************************************************************************/


		typedef union ii_iprte0b_u {
		uint64_t ii_iprte0b_regval;
		struct {
		@@ -1944,7 +1878,6 @@ typedef union ii_iprte0b_u {
		} ii_iprte0b_fld_s;
		} ii_iprte0b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1965,7 +1898,6 @@ typedef union ii_iprte1b_u {
		} ii_iprte1b_fld_s;
		} ii_iprte1b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -1986,7 +1918,6 @@ typedef union ii_iprte2b_u {
		} ii_iprte2b_fld_s;
		} ii_iprte2b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -2007,7 +1938,6 @@ typedef union ii_iprte3b_u {
		} ii_iprte3b_fld_s;
		} ii_iprte3b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -2028,7 +1958,6 @@ typedef union ii_iprte4b_u {
		} ii_iprte4b_fld_s;
		} ii_iprte4b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -2049,7 +1978,6 @@ typedef union ii_iprte5b_u {
		} ii_iprte5b_fld_s;
		} ii_iprte5b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -2071,7 +1999,6 @@ typedef union ii_iprte6b_u {
		} ii_iprte6b_fld_s;
		} ii_iprte6b_u_t;


		/************************************************************************
		* *
		* There are 8 instances of this register. This register contains *
		@@ -2092,7 +2019,6 @@ typedef union ii_iprte7b_u {
		} ii_iprte7b_fld_s;
		} ii_iprte7b_u_t;


		/************************************************************************
		* *
		* Description: SHub II contains a feature which did not exist in *
		@@ -2122,7 +2048,6 @@ typedef union ii_ipdr_u {
		} ii_ipdr_fld_s;
		} ii_ipdr_u_t;


		/************************************************************************
		* *
		* A write to this register causes a CRB entry to be returned to the *
		@@ -2149,7 +2074,6 @@ typedef union ii_icdr_u {
		} ii_icdr_fld_s;
		} ii_icdr_u_t;


		/************************************************************************
		* *
		* This register provides debug access to two FIFOs inside of II. *
		@@ -2178,7 +2102,6 @@ typedef union ii_ifdr_u {
		} ii_ifdr_fld_s;
		} ii_ifdr_u_t;


		/************************************************************************
		* *
		* This register allows the II to become sluggish in removing *
		@@ -2200,7 +2123,6 @@ typedef union ii_iiap_u {
		} ii_iiap_fld_s;
		} ii_iiap_u_t;


		/************************************************************************
		* *
		* This register allows several parameters of CRB operation to be *
		@@ -2230,7 +2152,6 @@ typedef union ii_icmr_u {
		} ii_icmr_fld_s;
		} ii_icmr_u_t;


		/************************************************************************
		* *
		* This register allows control of the table portion of the CRB *
		@@ -2250,7 +2171,6 @@ typedef union ii_iccr_u {
		} ii_iccr_fld_s;
		} ii_iccr_u_t;


		/************************************************************************
		* *
		* This register allows the maximum timeout value to be programmed. *
		@@ -2265,7 +2185,6 @@ typedef union ii_icto_u {
		} ii_icto_fld_s;
		} ii_icto_u_t;


		/************************************************************************
		* *
		* This register allows the timeout prescalar to be programmed. An *
		@@ -2285,7 +2204,6 @@ typedef union ii_ictp_u {
		} ii_ictp_fld_s;
		} ii_ictp_u_t;


		/************************************************************************
		* *
		* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
		@@ -2321,7 +2239,6 @@ typedef union ii_icrb0_a_u {
		} ii_icrb0_a_fld_s;
		} ii_icrb0_a_u_t;


		/************************************************************************
		* *
		* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
		@@ -2359,7 +2276,6 @@ typedef union ii_icrb0_b_u {
		} ii_icrb0_b_fld_s;
		} ii_icrb0_b_u_t;


		/************************************************************************
		* *
		* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
		@@ -2384,7 +2300,6 @@ typedef union ii_icrb0_c_u {
		} ii_icrb0_c_fld_s;
		} ii_icrb0_c_u_t;


		/************************************************************************
		* *
		* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
		@@ -2406,7 +2321,6 @@ typedef union ii_icrb0_d_u {
		} ii_icrb0_d_fld_s;
		} ii_icrb0_d_u_t;


		/************************************************************************
		* *
		* Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
		@@ -2428,7 +2342,6 @@ typedef union ii_icrb0_e_u {
		} ii_icrb0_e_fld_s;
		} ii_icrb0_e_u_t;


		/************************************************************************
		* *
		* This register contains the lower 64 bits of the header of the *
		@@ -2447,7 +2360,6 @@ typedef union ii_icsml_u {
		} ii_icsml_fld_s;
		} ii_icsml_u_t;


		/************************************************************************
		* *
		* This register contains the middle 64 bits of the header of the *
		@@ -2464,7 +2376,6 @@ typedef union ii_icsmm_u {
		} ii_icsmm_fld_s;
		} ii_icsmm_u_t;


		/************************************************************************
		* *
		* This register contains the microscopic state, all the inputs to *
		@@ -2519,7 +2430,6 @@ typedef union ii_icsmh_u {
		} ii_icsmh_fld_s;
		} ii_icsmh_u_t;


		/************************************************************************
		* *
		* The Shub DEBUG unit provides a 3-bit selection signal to the *
		@@ -2540,7 +2450,6 @@ typedef union ii_idbss_u {
		} ii_idbss_fld_s;
		} ii_idbss_u_t;


		/************************************************************************
		* *
		* Description: This register is used to set up the length for a *
		@@ -2567,7 +2476,6 @@ typedef union ii_ibls0_u {
		} ii_ibls0_fld_s;
		} ii_ibls0_u_t;


		/************************************************************************
		* *
		* This register should be loaded before a transfer is started. The *
		@@ -2587,7 +2495,6 @@ typedef union ii_ibsa0_u {
		} ii_ibsa0_fld_s;
		} ii_ibsa0_u_t;


		/************************************************************************
		* *
		* This register should be loaded before a transfer is started. The *
		@@ -2607,7 +2514,6 @@ typedef union ii_ibda0_u {
		} ii_ibda0_fld_s;
		} ii_ibda0_u_t;


		/************************************************************************
		* *
		* Writing to this register sets up the attributes of the transfer *
		@@ -2632,7 +2538,6 @@ typedef union ii_ibct0_u {
		} ii_ibct0_fld_s;
		} ii_ibct0_u_t;


		/************************************************************************
		* *
		* This register contains the address to which the WINV is sent. *
		@@ -2649,7 +2554,6 @@ typedef union ii_ibna0_u {
		} ii_ibna0_fld_s;
		} ii_ibna0_u_t;


		/************************************************************************
		* *
		* This register contains the programmable level as well as the node *
		@@ -2669,7 +2573,6 @@ typedef union ii_ibia0_u {
		} ii_ibia0_fld_s;
		} ii_ibia0_u_t;


		/************************************************************************
		* *
		* Description: This register is used to set up the length for a *
		@@ -2696,7 +2599,6 @@ typedef union ii_ibls1_u {
		} ii_ibls1_fld_s;
		} ii_ibls1_u_t;


		/************************************************************************
		* *
		* This register should be loaded before a transfer is started. The *
		@@ -2716,7 +2618,6 @@ typedef union ii_ibsa1_u {
		} ii_ibsa1_fld_s;
		} ii_ibsa1_u_t;


		/************************************************************************
		* *
		* This register should be loaded before a transfer is started. The *
		@@ -2736,7 +2637,6 @@ typedef union ii_ibda1_u {
		} ii_ibda1_fld_s;
		} ii_ibda1_u_t;


		/************************************************************************
		* *
		* Writing to this register sets up the attributes of the transfer *
		@@ -2761,7 +2661,6 @@ typedef union ii_ibct1_u {
		} ii_ibct1_fld_s;
		} ii_ibct1_u_t;


		/************************************************************************
		* *
		* This register contains the address to which the WINV is sent. *
		@@ -2778,7 +2677,6 @@ typedef union ii_ibna1_u {
		} ii_ibna1_fld_s;
		} ii_ibna1_u_t;


		/************************************************************************
		* *
		* This register contains the programmable level as well as the node *
		@@ -2798,7 +2696,6 @@ typedef union ii_ibia1_u {
		} ii_ibia1_fld_s;
		} ii_ibia1_u_t;


		/************************************************************************
		* *
		* This register defines the resources that feed information into *
		@@ -2824,7 +2721,6 @@ typedef union ii_ipcr_u {
		} ii_ipcr_fld_s;
		} ii_ipcr_u_t;


		/************************************************************************
		* *
		* *
		@@ -2839,9 +2735,7 @@ typedef union ii_ippr_u {
		} ii_ippr_fld_s;
		} ii_ippr_u_t;



		/**************************************************************************
		/************************************************************************
		* *
		* The following defines which were not formed into structures are *
		* probably indentical to another register, and the name of the *
		@@ -2919,8 +2813,7 @@ typedef union ii_ippr_u {
		* IIO_ICRBE_D IIO_ICRB0_D *
		* IIO_ICRBE_E IIO_ICRB0_E *
		* *
		**************************************************************************/

		************************************************************************/

		/*
		* Slightly friendlier names for some common registers.
		@@ -2960,7 +2853,7 @@ typedef union ii_ippr_u {
		#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
		#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */

		#define IIO_NUM_IPRBS (9)
		#define IIO_NUM_IPRBS 9

		#define IIO_LLP_CSR_IS_UP 0x00002000
		#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
		@@ -2990,7 +2883,6 @@ typedef union ii_ippr_u {
		#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
		#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)


		/* names used in shub diags */
		#define IIO_BASE_BTE0 IIO_IBLS_0
		#define IIO_BASE_BTE1 IIO_IBLS_1
		@@ -3005,7 +2897,6 @@ typedef union ii_ippr_u {
		(_x) : \
		(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )


		/* GFX Flow Control Node/Widget Register */
		#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
		#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
		@@ -3025,7 +2916,6 @@ typedef union ii_ippr_u {
		(((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) \| \
		(((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))


		/* Scratch registers (all bits available) */
		#define IIO_SCRATCH_REG0 IIO_ISCR0
		#define IIO_SCRATCH_REG1 IIO_ISCR1
		@@ -3242,16 +3132,16 @@ typedef union ii_ippr_u {
		/*
		* IIO CRB control register Fields: IIO_ICCR
		*/
		#define IIO_ICCR_PENDING (0x10000)
		#define IIO_ICCR_CMD_MASK (0xFF)
		#define IIO_ICCR_CMD_SHFT (7)
		#define IIO_ICCR_CMD_NOP (0x0) /* No Op */
		#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */
		#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */
		#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory
		#define IIO_ICCR_PENDING 0x10000
		#define IIO_ICCR_CMD_MASK 0xFF
		#define IIO_ICCR_CMD_SHFT 7
		#define IIO_ICCR_CMD_NOP 0x0 /* No Op */
		#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */
		#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */
		#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory
		* via a WB
		*/
		#define IIO_ICCR_CMD_FLUSH (0x800)
		#define IIO_ICCR_CMD_FLUSH 0x800

		/*
		*
		@@ -3324,7 +3214,6 @@ typedef ii_icrb0_c_u_t icrbc_t;
		#define c_source ii_icrb0_c_fld_s.ic_source
		#define c_regvalue ii_icrb0_c_regval


		typedef ii_icrb0_d_u_t icrbd_t;
		#define d_sleep ii_icrb0_d_fld_s.id_sleep
		#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
		@@ -3341,7 +3230,6 @@ typedef ii_icrb0_e_u_t icrbe_t;
		#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
		#define e_regvalue ii_icrb0_e_regval


		/* Number of widgets supported by shub */
		#define HUB_NUM_WIDGET 9
		#define HUB_WIDGET_ID_MIN 0x8
		@@ -3369,8 +3257,8 @@ typedef ii_icrb0_e_u_t icrbe_t;

		#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
		#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
		#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */
		#define IIO_WSTAT_TXRETRY_SHFT (16)
		#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */
		#define IIO_WSTAT_TXRETRY_SHFT 16
		#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
		IIO_WSTAT_TXRETRY_MASK)

		@@ -3438,10 +3326,7 @@ performance registers */
		typedef union io_perf_sel {
		uint64_t perf_sel_reg;
		struct {
		uint64_t perf_ippr0 : 4,
		perf_ippr1 : 4,
		perf_icct : 8,
		perf_rsvd : 48;
		uint64_t perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
		} perf_sel_bits;
		} io_perf_sel_t;

		@@ -3451,9 +3336,7 @@ typedef union io_perf_sel {
		typedef union io_perf_cnt {
		uint64_t perf_cnt;
		struct {
		uint64_t perf_cnt : 20,
		perf_rsvd2 : 12,
		perf_rsvd1 : 32;
		uint64_t perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
		} perf_cnt_bits;

		} io_perf_cnt_t;
		@@ -3473,4 +3356,3 @@ typedef union iprte_a {
		} iprte_a_t;

		#endif /* _ASM_IA64_SN_SHUBIO_H */