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Commit 43a7d2d1 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: group r6xx/r7xx newly sequential blit state 



group state that is emitted sequentially into fewer packets.
This saves a number of dwords.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent d0623a3e

drivers/gpu/drm/radeon/r600_blit_shaders.c

+35 −203
Original line number Diff line number Diff line
@@ -109,22 +109,13 @@ const u32 r6xx_default_state[] = 
	0x00000351,

	0x0000aa00, /* DB_ALPHA_TO_MASK */



	0xc0036900,

	0xc00f6900,

	0x00000100,

	0x00000800, /* VGT_MAX_VTX_INDX */

	0x00000000, /* VGT_MIN_VTX_INDX */

	0x00000000, /* VGT_INDX_OFFSET */



	0xc0016900,

	0x00000103,

	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */



	0xc0016900,

	0x00000104,

	0x00000000, /* SX_ALPHA_TEST_CONTROL */



	0xc0076900,

	0x00000105,

	0x00000000, /* CB_BLEND_RED */

	0x00000000,

	0x00000000,
@@ -132,16 +123,19 @@ const u32 r6xx_default_state[] = 
	0x00000000, /* CB_FOG_RED */

	0x00000000,

	0x00000000,



	0xc0026900,

	0x0000010c,

	0x00000000, /* DB_STENCILREFMASK */

	0x00000000, /* DB_STENCILREFMASK_BF */



	0xc0016900,

	0x0000010e,

	0x00000000, /* SX_ALPHA_REF */



	0xc0066900,

	0x0000010f,

	0x00000000, /* PA_CL_VPORT_XSCALE */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0046900,

	0x0000030c,

	0x01000000, /* CB_CLRCMP_CNTL */
@@ -240,41 +234,20 @@ const u32 r6xx_default_state[] = 
	0x00000000,

	0x3f800000,



	0xc0016900,

	0xc0026900,

	0x00000292,

	0x00000000, /* PA_SC_MPASS_PS_CNTL */



	0xc0016900,

	0x00000293,

	0x00004010, /* PA_SC_MODE_CNTL */



	0xc0066900,

	0x0000010f,

	0x00000000, /* PA_CL_VPORT_0_XSCALE */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0026900,

	0xc0096900,

	0x00000300,

	0x00000000, /* PA_SC_LINE_CNTL */

	0x00000000, /* PA_SC_AA_CONFIG */



	0xc0016900,

	0x00000302,

	0x0000002d, /* PA_SU_VTX_CNTL */



	0xc0046900,

	0x00000303,

	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */

	0x3f800000,

	0x3f800000,

	0x3f800000,



	0xc0026900,

	0x00000307,

	0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */

	0x00000000,
@@ -282,28 +255,13 @@ const u32 r6xx_default_state[] = 
	0x00000312,

	0xffffffff, /* PA_SC_AA_MASK */



	0xc0016900,

	0xc0066900,

	0x0000037e,

	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */



	0xc0016900,

	0x0000037f,

	0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */



	0xc0016900,

	0x00000380,

	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */



	0xc0016900,

	0x00000381,

	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */



	0xc0016900,

	0x00000382,

	0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */



	0xc0016900,

	0x00000383,

	0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */



	0xc0046900,
@@ -330,29 +288,14 @@ const u32 r6xx_default_state[] = 
	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */

	0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */



	0xc0026900,

	0xc0116900,

	0x00000280,

	0x00000000, /* PA_SU_POINT_SIZE */

	0x00000000, /* PA_SU_POINT_MINMAX */



	0xc0016900,

	0x00000282,

	0x00000008, /* PA_SU_LINE_CNTL */



	0xc0016900,

	0x00000283,

	0x00000000, /* PA_SC_LINE_STIPPLE */



	0xc0016900,

	0x00000284,

	0x00000000, /* VGT_OUTPUT_PATH_CNTL */



	0xc0016900,

	0x00000285,

	0x00000000, /* VGT_HOS_CNTL */



	0xc00a6900,

	0x00000286,

	0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */

	0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */

	0x00000000, /* VGT_HOS_REUSE_DEPTH */
@@ -363,9 +306,6 @@ const u32 r6xx_default_state[] = 
	0x00000000, /* VGT_GROUP_VECT_1_CNTL */

	0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */

	0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */



	0xc0016900,

	0x00000290,

	0x00000000, /* VGT_GS_MODE */



	0xc0016900,
@@ -386,37 +326,19 @@ const u32 r6xx_default_state[] = 
	0x000002c8,

	0x00000000, /* VGT_STRMOUT_BUFFER_EN */



	0xc0016900,

	0xc0076900,

	0x00000202,

	0x00cc0000, /* CB_COLOR_CONTROL */



	0xc0016900,

	0x00000203,

	0x00000210, /* DB_SHADER_CNTL */



	0xc0016900,

	0x00000204,

	0x00010000, /* PA_CL_CLIP_CNTL */



	0xc0016900,

	0x00000205,

	0x00000244, /* PA_SU_SC_MODE_CNTL */



	0xc0016900,

	0x00000206,

	0x00000100, /* PA_CL_VTE_CNTL */



	0xc0026900,

	0x00000207,

	0x00000000, /* PA_CL_VS_OUT_CNTL */

	0x00000000, /* PA_CL_NANINF_CNTL */



	0xc0016900,

	0xc0026900,

	0x0000008e,

	0x0000000f, /* CB_TARGET_MASK */



	0xc0016900,

	0x0000008f,

	0x0000000f, /* CB_SHADER_MASK */



	0xc0016900,
@@ -431,21 +353,12 @@ const u32 r6xx_default_state[] = 
	0x00000191,

	0x00000b00, /* SPI_PS_INPUT_CNTL_0 */



	0xc0016900,

	0xc0056900,

	0x000001b1,

	0x00000000, /* SPI_VS_OUT_CONFIG */



	0xc0016900,

	0x000001b2,

	0x00000000, /* SPI_THREAD_GROUPING */



	0xc0026900,

	0x000001b3,

	0x00000001, /* SPI_PS_IN_CONTROL_0 */

	0x00000000, /* SPI_PS_IN_CONTROL_1 */



	0xc0016900,

	0x000001b5,

	0x00000000, /* SPI_INTERP_CONTROL_0 */



	0xc0036e00, /* SET_SAMPLER */
@@ -524,36 +437,33 @@ const u32 r7xx_default_state[] = 
	0x00000351,

	0x0000aa00, /* DB_ALPHA_TO_MASK */



	0xc0036900,

	0xc0096900,

	0x00000100,

	0x00000800, /* VGT_MAX_VTX_INDX */

	0x00000000, /* VGT_MIN_VTX_INDX */

	0x00000000, /* VGT_INDX_OFFSET */



	0xc0016900,

	0x00000103,

	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */



	0xc0016900,

	0x00000104,

	0x00000000, /* SX_ALPHA_TEST_CONTROL */



	0xc0046900,

	0x00000105,

	0x00000000, /* CB_BLEND_RED */

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0026900,

	0xc0036900,

	0x0000010c,

	0x00000000, /* DB_STENCILREFMASK */

	0x00000000, /* DB_STENCILREFMASK_BF */



	0xc0016900,

	0x0000010e,

	0x00000000, /* SX_ALPHA_REF */



	0xc0066900,

	0x0000010f,

	0x00000000, /* PA_CL_VPORT_XSCALE */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0046900,

	0x0000030c, /* CB_CLRCMP_CNTL */

	0x01000000,
@@ -645,41 +555,20 @@ const u32 r7xx_default_state[] = 
	0x00000000,

	0x3f800000,



	0xc0016900,

	0xc0026900,

	0x00000292,

	0x00000000, /* PA_SC_MPASS_PS_CNTL */



	0xc0016900,

	0x00000293,

	0x00514000, /* PA_SC_MODE_CNTL */



	0xc0066900,

	0x0000010f,

	0x00000000, /* PA_CL_VPORT_0_XSCALE */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0026900,

	0xc0096900,

	0x00000300,

	0x00000000, /* PA_SC_LINE_CNTL */

	0x00000000, /* PA_SC_AA_CONFIG */



	0xc0016900,

	0x00000302,

	0x0000002d, /* PA_SU_VTX_CNTL */



	0xc0046900,

	0x00000303,

	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */

	0x3f800000,

	0x3f800000,

	0x3f800000,



	0xc0026900,

	0x00000307,

	0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */

	0x00000000,
@@ -687,28 +576,13 @@ const u32 r7xx_default_state[] = 
	0x00000312,

	0xffffffff, /* PA_SC_AA_MASK */



	0xc0016900,

	0xc0066900,

	0x0000037e,

	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */



	0xc0016900,

	0x0000037f,

	0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */



	0xc0016900,

	0x00000380,

	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */



	0xc0016900,

	0x00000381,

	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */



	0xc0016900,

	0x00000382,

	0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */



	0xc0016900,

	0x00000383,

	0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */



	0xc0046900,
@@ -735,25 +609,13 @@ const u32 r7xx_default_state[] = 
	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */

	0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */



	0xc0026900,

	0xc0116900,

	0x00000280,

	0x00000000, /* PA_SU_POINT_SIZE */

	0x00000000, /* PA_SU_POINT_MINMAX */



	0xc0016900,

	0x00000282,

	0x00000008, /* PA_SU_LINE_CNTL */



	0xc0016900,

	0x00000283,

	0x00000000, /* PA_SC_LINE_STIPPLE */



	0xc0016900,

	0x00000284,

	0x00000000, /* VGT_OUTPUT_PATH_CNTL */



	0xc00b6900,

	0x00000285,

	0x00000000, /* VGT_HOS_CNTL */

	0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */

	0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
@@ -765,9 +627,6 @@ const u32 r7xx_default_state[] = 
	0x00000000, /* VGT_GROUP_VECT_1_CNTL */

	0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */

	0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */



	0xc0016900,

	0x00000290,

	0x00000000, /* VGT_GS_MODE */



	0xc0016900,
@@ -788,37 +647,19 @@ const u32 r7xx_default_state[] = 
	0x000002c8,

	0x00000000, /* VGT_STRMOUT_BUFFER_EN */



	0xc0016900,

	0xc0076900,

	0x00000202,

	0x00cc0000, /* CB_COLOR_CONTROL */



	0xc0016900,

	0x00000203,

	0x00000210, /* DB_SHADER_CNTL */



	0xc0016900,

	0x00000204,

	0x00010000, /* PA_CL_CLIP_CNTL */



	0xc0016900,

	0x00000205,

	0x00000244, /* PA_SU_SC_MODE_CNTL */



	0xc0016900,

	0x00000206,

	0x00000100, /* PA_CL_VTE_CNTL */



	0xc0026900,

	0x00000207,

	0x00000000, /* PA_CL_VS_OUT_CNTL */

	0x00000000, /* PA_CL_NANINF_CNTL */



	0xc0016900,

	0xc0026900,

	0x0000008e,

	0x0000000f, /* CB_TARGET_MASK */



	0xc0016900,

	0x0000008f,

	0x0000000f, /* CB_SHADER_MASK */



	0xc0016900,
@@ -833,21 +674,12 @@ const u32 r7xx_default_state[] = 
	0x00000191,

	0x00000b00, /* SPI_PS_INPUT_CNTL_0 */



	0xc0016900,

	0xc0056900,

	0x000001b1,

	0x00000000, /* SPI_VS_OUT_CONFIG */



	0xc0016900,

	0x000001b2,

	0x00000001, /* SPI_THREAD_GROUPING */



	0xc0026900,

	0x000001b3,

	0x00000001, /* SPI_PS_IN_CONTROL_0 */

	0x00000000, /* SPI_PS_IN_CONTROL_1 */



	0xc0016900,

	0x000001b5,

	0x00000000, /* SPI_INTERP_CONTROL_0 */



	0xc0036e00, /* SET_SAMPLER */