ARM: LPC32XX: Initial arch header files

/*

 * arch/arm/mach-lpc32xx/include/mach/clkdev.h

 *

 * Author: Kevin Wells <kevin.wells@nxp.com>

 *

 * Copyright (C) 2010 NXP Semiconductors

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef __ASM_ARCH_CLKDEV_H

#define __ASM_ARCH_CLKDEV_H

#define __clk_get(clk) ({ 1; })

#define __clk_put(clk) do { } while (0)

#endif

/*

 * arch/arm/mach-lpc32xx/include/mach/gpio.h

 *

 * Author: Kevin Wells <kevin.wells@nxp.com>

 *

 * Copyright (C) 2010 NXP Semiconductors

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef __ASM_ARCH_GPIO_H

#define __ASM_ARCH_GPIO_H

#include <asm-generic/gpio.h>

/*

 * Note!

 * Muxed GP pins need to be setup to the GP state in the board level

 * code prior to using this driver.

 * GPI pins : 28xP3 group

 * GPO pins : 24xP3 group

 * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group

 */

#define LPC32XX_GPIO_P0_MAX 8

#define LPC32XX_GPIO_P1_MAX 24

#define LPC32XX_GPIO_P2_MAX 13

#define LPC32XX_GPIO_P3_MAX 6

#define LPC32XX_GPI_P3_MAX 28

#define LPC32XX_GPO_P3_MAX 24

#define LPC32XX_GPIO_P0_GRP 0

#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)

#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)

#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)

#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)

#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)

/*

 * A specific GPIO can be selected with this macro

 * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)

 * See the LPC32x0 User's guide for GPIO group numbers

 */

#define LPC32XX_GPIO(x, y) ((x) + (y))

static inline int gpio_get_value(unsigned gpio)

{

	return __gpio_get_value(gpio);

}

static inline void gpio_set_value(unsigned gpio, int value)

{

	__gpio_set_value(gpio, value);

}

static inline int gpio_cansleep(unsigned gpio)

{

	return __gpio_cansleep(gpio);

}

static inline int gpio_to_irq(unsigned gpio)

{

	return __gpio_to_irq(gpio);

}

#endif

/*

 * arch/arm/mach-lpc32xx/include/mach/hardware.h

 *

 * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef __ASM_ARCH_HARDWARE_H

#define __ASM_ARCH_HARDWARE_H

/*

 * Start of virtual addresses for IO devices

 */

#define IO_BASE		0xF0000000

/*

 * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0

 */

#define IO_ADDRESS(x)	(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\

			 IO_BASE)

#define io_p2v(x)	((void __iomem *) (unsigned long) IO_ADDRESS(x))

#define io_v2p(x)	((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))

#endif

/*

 * PNX4008-specific tweaks for I2C IP3204 block

 *

 * Author: Vitaly Wool <vwool@ru.mvista.com>

 *

 * 2005 (c) MontaVista Software, Inc. This file is licensed under

 * the terms of the GNU General Public License version 2. This program

 * is licensed "as is" without any warranty of any kind, whether express

 * or implied.

 */

#ifndef __ASM_ARCH_I2C_H

#define __ASM_ARCH_I2C_H

enum {

	mstatus_tdi = 0x00000001,

	mstatus_afi = 0x00000002,

	mstatus_nai = 0x00000004,

	mstatus_drmi = 0x00000008,

	mstatus_active = 0x00000020,

	mstatus_scl = 0x00000040,

	mstatus_sda = 0x00000080,

	mstatus_rff = 0x00000100,

	mstatus_rfe = 0x00000200,

	mstatus_tff = 0x00000400,

	mstatus_tfe = 0x00000800,

};

enum {

	mcntrl_tdie = 0x00000001,

	mcntrl_afie = 0x00000002,

	mcntrl_naie = 0x00000004,

	mcntrl_drmie = 0x00000008,

	mcntrl_daie = 0x00000020,

	mcntrl_rffie = 0x00000040,

	mcntrl_tffie = 0x00000080,

	mcntrl_reset = 0x00000100,

	mcntrl_cdbmode = 0x00000400,

};

enum {

	rw_bit = 1 << 0,

	start_bit = 1 << 8,

	stop_bit = 1 << 9,

};

#define I2C_REG_RX(a)	((a)->ioaddr)		/* Rx FIFO reg (RO) */

#define I2C_REG_TX(a)	((a)->ioaddr)		/* Tx FIFO reg (WO) */

#define I2C_REG_STS(a)	((a)->ioaddr + 0x04)	/* Status reg (RO) */

#define I2C_REG_CTL(a)	((a)->ioaddr + 0x08)	/* Ctl reg */

#define I2C_REG_CKL(a)	((a)->ioaddr + 0x0c)	/* Clock divider low */

#define I2C_REG_CKH(a)	((a)->ioaddr + 0x10)	/* Clock divider high */

#define I2C_REG_ADR(a)	((a)->ioaddr + 0x14)	/* I2C address */

#define I2C_REG_RFL(a)	((a)->ioaddr + 0x18)	/* Rx FIFO level (RO) */

#define I2C_REG_TFL(a)	((a)->ioaddr + 0x1c)	/* Tx FIFO level (RO) */

#define I2C_REG_RXB(a)	((a)->ioaddr + 0x20)	/* Num of bytes Rx-ed (RO) */

#define I2C_REG_TXB(a)	((a)->ioaddr + 0x24)	/* Num of bytes Tx-ed (RO) */

#define I2C_REG_TXS(a)	((a)->ioaddr + 0x28)	/* Tx slave FIFO (RO) */

#define I2C_REG_STFL(a)	((a)->ioaddr + 0x2c)	/* Tx slave FIFO level (RO) */

#define I2C_CHIP_NAME		"PNX4008-I2C"

#endif				/* __ASM_ARCH_I2C_H */

/*

 * arch/arm/mach-lpc32xx/include/mach/io.h

 *

 * Author: Kevin Wells <kevin.wells@nxp.com>

 *

 * Copyright (C) 2010 NXP Semiconductors

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef __ASM_ARM_ARCH_IO_H

#define __ASM_ARM_ARCH_IO_H

#define IO_SPACE_LIMIT	0xffffffff

#define __io(a)		__typesafe_io(a)

#define __mem_pci(a)	(a)

#endif