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Commit 4377d9d9 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "usb: dwc3: msm: Add option to bypass SMMU stage 1" into msm-4.9

parents 12a45c77 283cece2

Documentation/devicetree/bindings/usb/msm-ssusb.txt

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ Optional properties : 
  event buffers. 1 event buffer is needed per h/w accelerated endpoint.

- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs,

	which is used as a vote by driver to get max performance in perf mode.

- qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation.



Sub nodes:

- Sub node for "DWC3- USB3 controller".

drivers/usb/dwc3/dwc3-msm.c

+10 −1
Original line number Diff line number Diff line
@@ -2822,7 +2822,7 @@ static int dwc3_msm_extcon_register(struct dwc3_msm *mdwc) 
static int dwc3_msm_init_iommu(struct dwc3_msm *mdwc)

{

	struct device_node *node = mdwc->dev->of_node;

	int atomic_ctx = 1;

	int atomic_ctx = 1, s1_bypass;

	int ret;



	if (!of_property_read_bool(node, "iommus"))
@@ -2846,6 +2846,15 @@ static int dwc3_msm_init_iommu(struct dwc3_msm *mdwc) 
		goto release_mapping;

	}



	s1_bypass = of_property_read_bool(node, "qcom,smmu-s1-bypass");

	ret = iommu_domain_set_attr(mdwc->iommu_map->domain,

			DOMAIN_ATTR_S1_BYPASS, &s1_bypass);

	if (ret) {

		dev_err(mdwc->dev, "IOMMU set s1 bypass (%d) failed (%d)\n",

			s1_bypass, ret);

		goto release_mapping;

	}



	ret = arm_iommu_attach_device(mdwc->dev, mdwc->iommu_map);

	if (ret) {

		dev_err(mdwc->dev, "IOMMU attach failed (%d)\n", ret);