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Commit 4310e908 authored by Keerthy's avatar Keerthy Committed by Tony Lindgren
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ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck 



Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.

Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.

Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.

So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input
of apll.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 147e5413

arch/arm/boot/dts/dra7xx-clocks.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1152,7 +1152,7 @@ 


	apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {

		compatible = "ti,mux-clock";

		clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;

		clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;

		#clock-cells = <0>;

		reg = <0x021c 0x4>;

		ti,bit-shift = <7>;