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Commit 42fc6370 authored by Ondrej Zary's avatar Ondrej Zary Committed by Martin K. Petersen
Browse files

ncr5380: Fix wait for 53C80 registers registers after PDMA 



The check for 53C80 registers accessibility was commented out because
it was broken (inverted). Fix and enable it.

Signed-off-by: default avatarOndrej Zary <linux@rainbow-software.org>
Signed-off-by: default avatarFinn Thain <fthain@telegraphics.com.au>
Reviewed-by: default avatarHannes Reinecke <hare@suse.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent aeb51152

drivers/scsi/g_NCR5380.c

+6 −31
Original line number Diff line number Diff line
@@ -609,14 +609,10 @@ static inline int NCR5380_pread(struct Scsi_Host *instance, unsigned char *dst, 
	if (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ))

		printk("53C400r: no 53C80 gated irq after transfer");



#if 0

	/*

	 *	DON'T DO THIS - THEY NEVER ARRIVE!

	 */

	printk("53C400r: Waiting for 53C80 registers\n");

	while (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)

	/* wait for 53C80 registers to be available */

	while (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG))

		;

#endif



	if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER))

		printk(KERN_ERR "53C400r: no end dma signal\n");
@@ -638,7 +634,6 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src, 
	struct NCR5380_hostdata *hostdata = shost_priv(instance);

	int blocks = len / 128;

	int start = 0;

	int i;



	NCR5380_write(hostdata->c400_ctl_status, CSR_BASE);

	NCR5380_write(hostdata->c400_blk_cnt, blocks);
@@ -687,36 +682,16 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src, 
		blocks--;

	}



#if 0

	printk("53C400w: waiting for registers to be available\n");

	THEY NEVER DO ! while (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG);

	printk("53C400w: Got em\n");

#endif



	/* Let's wait for this instead - could be ugly */

	/* All documentation says to check for this. Maybe my hardware is too

	 * fast. Waiting for it seems to work fine! KLL

	 */

	while (!(i = NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ)) {

	/* wait for 53C80 registers to be available */

	while (!(NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG)) {

		udelay(4); /* DTC436 chip hangs without this */

		/* FIXME - no timeout */

	}



	/*

	 * I know. i is certainly != 0 here but the loop is new. See previous

	 * comment.

	 */

	if (i) {

		if (!((i = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER))

			printk(KERN_ERR "53C400w: No END OF DMA bit - WHOOPS! BASR=%0x\n", i);

	} else

		printk(KERN_ERR "53C400w: no 53C80 gated irq after transfer (last block)\n");



#if 0

	if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) {

		printk(KERN_ERR "53C400w: no end dma signal\n");

	}

#endif



	while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT))

		; 	// TIMEOUT

	return 0;